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#ifndef _ALTERA_HPS_0_H_
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#define _ALTERA_HPS_0_H_
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/*
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* This file was automatically generated by the swinfo2header utility.
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*
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* Created from SOPC Builder system 'soc_system' in
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* file './soc_system.sopcinfo'.
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*/
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/*
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* This file contains macros for module 'hps_0' and devices
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* connected to the following masters:
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* h2f_axi_master
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* h2f_lw_axi_master
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*
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* Do not include this header file and another header file created for a
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* different module or master group at the same time.
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* Doing so may result in duplicate macro names.
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* Instead, use the system header file which has macros with unique names.
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*/
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/*
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* Macros for device 'onchip_memory2_0', class 'altera_avalon_onchip_memory2'
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* The macros are prefixed with 'ONCHIP_MEMORY2_0_'.
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* The prefix is the slave descriptor.
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*/
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#define ONCHIP_MEMORY2_0_COMPONENT_TYPE altera_avalon_onchip_memory2
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#define ONCHIP_MEMORY2_0_COMPONENT_NAME onchip_memory2_0
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#define ONCHIP_MEMORY2_0_BASE 0x0
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#define ONCHIP_MEMORY2_0_SPAN 4096
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#define ONCHIP_MEMORY2_0_END 0xfff
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#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
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#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
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#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
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#define ONCHIP_MEMORY2_0_DUAL_PORT 0
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#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE AUTO
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#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE soc_system_onchip_memory2_0
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#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 1
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#define ONCHIP_MEMORY2_0_INSTANCE_ID NONE
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#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0
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#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE AUTO
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#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE DONT_CARE
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#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
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#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
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#define ONCHIP_MEMORY2_0_SIZE_VALUE 4096
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#define ONCHIP_MEMORY2_0_WRITABLE 1
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#define ONCHIP_MEMORY2_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
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#define ONCHIP_MEMORY2_0_MEMORY_INFO_GENERATE_DAT_SYM 1
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#define ONCHIP_MEMORY2_0_MEMORY_INFO_GENERATE_HEX 1
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#define ONCHIP_MEMORY2_0_MEMORY_INFO_HAS_BYTE_LANE 0
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#define ONCHIP_MEMORY2_0_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
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#define ONCHIP_MEMORY2_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
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#define ONCHIP_MEMORY2_0_MEMORY_INFO_MEM_INIT_FILENAME soc_system_onchip_memory2_0
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/*
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* Macros for device 'reg_read_0', class 'reg_read'
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* The macros are prefixed with 'REG_READ_0_'.
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* The prefix is the slave descriptor.
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*/
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#define REG_READ_0_COMPONENT_TYPE reg_read
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#define REG_READ_0_COMPONENT_NAME reg_read_0
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#define REG_READ_0_BASE 0x0
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#define REG_READ_0_SPAN 16
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#define REG_READ_0_END 0xf
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/*
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* Macros for device 'reg32_write_0', class 'reg32_write'
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* The macros are prefixed with 'REG32_WRITE_0_'.
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* The prefix is the slave descriptor.
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*/
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#define REG32_WRITE_0_COMPONENT_TYPE reg32_write
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#define REG32_WRITE_0_COMPONENT_NAME reg32_write_0
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#define REG32_WRITE_0_BASE 0x10
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#define REG32_WRITE_0_SPAN 16
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#define REG32_WRITE_0_END 0x1f
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#endif /* _ALTERA_HPS_0_H_ */
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