Révision 132
Ajouté par macolomban1 il y a plus de 6 ans
| branch/tag/bsp/sfr32c83.h | ||
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/************************************************************************
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* *
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* file name : definition of M32C/80's SFR *
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* *
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* Copyright, 2003 RENESAS TECHNOLOGY CORPORATION *
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* AND RENESAS SOLUTIONS CORPORATION *
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* *
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* Version : 1.01 ( 2002-06-28) *
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* 1.02 ( 2002-07-09) *
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* 1.03 ( 2002-09-19) *
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* change: *
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* delete same symbol name *
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* 1.04 ( 2003-10-15) *
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* change: *
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* pu32 pur3_addr.bit.b1 *
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* -> pu32 pur3_addr.bit.b2 *
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* pu33 pur3_addr.bit.b1 *
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* -> pu33 pur3_addr.bit.b3 *
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* pu34 pur3_addr.bit.b1 *
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* -> pu34 pur3_addr.bit.b4 *
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* pu35 pur3_addr.bit.b1 *
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* -> pu35 pur3_addr.bit.b5 *
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* pu36 pur3_addr.bit.b1 *
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* -> pu36 pur3_addr.bit.b6 *
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* pu37 pur3_addr.bit.b1 *
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* -> pu37 pur3_addr.bit.b7 *
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* pu42 pur4_addr.bit.b1 *
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* -> pu42 pur4_addr.bit.b2 *
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* pu43 pur4_addr.bit.b1 *
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* -> pu43 pur4_addr.bit.b3 *
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* *
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*************************************************************************/
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/*
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note:
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This data is a freeware that SFR for M32C/80 groups is described.
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Renesas Technology Corporation and Renesas Solutions Corporation
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assumes no responsibility for any damage that occurred by this data.
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*/
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/************************************************************************
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* declare SFR address *
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************************************************************************/
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#pragma ADDRESS pm0_addr 0004H /* Processor mode register 0 */
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#pragma ADDRESS pm1_addr 0005H /* Processor mode register 1 */
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#pragma ADDRESS cm0_addr 0006H /* System clock control register 0 */
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#pragma ADDRESS cm1_addr 0007H /* System clock control register 1 */
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#pragma ADDRESS wcr_addr 0008H /* Wait control register */
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#pragma ADDRESS aier_addr 0009H /* Address match interrupt enable register */
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#pragma ADDRESS prcr_addr 000aH /* Protect register */
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#pragma ADDRESS ds_addr 000bH /* External data bus width control register */
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#pragma ADDRESS mcd_addr 000cH /* Main clock division register */
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#pragma ADDRESS cm2_addr 000dH /* Oscillation stop detect register */
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#pragma ADDRESS wdts_addr 000eH /* Watchdog timer start register */
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#pragma ADDRESS wdc_addr 000fH /* Watchdog timer control register */
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#pragma ADDRESS rmad0_addr 0010H /* Address match interrupt register 0 */
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#pragma ADDRESS rmad1_addr 0014H /* Address match interrupt register 1 */
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#pragma ADDRESS plv_addr 0017H /* PLL VDC control register */
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#pragma ADDRESS rmad2_addr 0018H /* Address match interrupt register 2 */
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#pragma ADDRESS vdc0_addr 001bH /* VDC control register 0 */
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#pragma ADDRESS rmad3_addr 001cH /* Address match interrupt register 3 */
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#pragma ADDRESS vdc1_addr 001fH /* VDC control register 1 */
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#pragma ADDRESS eiad_addr 0020H /* Emulator Exclusive Use Interrupt Register */
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#pragma ADDRESS eitd_addr 0023H /* Emulator Exclusive Use Interrupt Distinction Register*/
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#pragma ADDRESS eprr_addr 0024H /* Emulator Exclusive Use Protect Register*/
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#pragma ADDRESS emu_addr 0025H /* Emulator Setting Register*/
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#pragma ADDRESS roa_addr 0030H /* ROM Area Setting Register*/
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#pragma ADDRESS dba_addr 0031H /* Debugging Monitor Setting Register*/
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#pragma ADDRESS exa0_addr 0032H /* Expansion Area Setting Register 0*/
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#pragma ADDRESS exa1_addr 0033H /* Expansion Area Setting Register 1*/
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#pragma ADDRESS exa2_addr 0034H /* Expansion Area Setting Register 2*/
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#pragma ADDRESS exa3_addr 0035H /* Expansion Area Setting Register 3*/
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#pragma ADDRESS dramcont_addr 0040H /* DRAM control register */
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#pragma ADDRESS refcnt_addr 0041H /* DRAM refresh interval set register */
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#pragma ADDRESS fmr2_addr 0055H /* Flash Memory Control Register 2*/
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#pragma ADDRESS fmr1_addr 0056H /* Flash Memory Control Register 2*/
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#pragma ADDRESS fmr0_addr 0057H /* Flash memory control register 0 */
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#pragma ADDRESS dm0ic_addr 0068H /* DMA0 interrupt control register */
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#pragma ADDRESS tb5ic_addr 0069H /* Timer B5 interrupt register */
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#pragma ADDRESS dm2ic_addr 006aH /* DMA2 interrupt register */
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#pragma ADDRESS s2ric_addr 006bH /* UART2 receive/ack interrupt control register */
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#pragma ADDRESS ta0ic_addr 006cH /* Timer A0 interrupt control register */
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#pragma ADDRESS s3ric_addr 006dH /* UART3 receive/ack interrupt control register */
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#pragma ADDRESS ta2ic_addr 006eH /* Timer A2 interrupt control register */
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#pragma ADDRESS s4ric_addr 006fH /* UART4 receive/ack interrupt control register */
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#pragma ADDRESS ta4ic_addr 0070H /* Timer A4 interrupt control register */
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#pragma ADDRESS bcn3ic_addr 0071H /* Bus collision (UART3) interrupt control register */
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#pragma ADDRESS bcn0ic_addr 0071H /* Bus collision (UART0) interrupt control register */
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#pragma ADDRESS s0ric_addr 0072H /* UART0 receive interrupt control register */
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#pragma ADDRESS ad0ic_addr 0073H /* A/D0 conversion interrupt control register */
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#pragma ADDRESS s1ric_addr 0074H /* UART1 receive interrupt control register */
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#pragma ADDRESS iio0ic_addr 0075H /* Intelligent I/O interrupt control register 0 */
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#pragma ADDRESS tb1ic_addr 0076H /* Timer B1 interrupt control register */
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#pragma ADDRESS iio2ic_addr 0077H /* Intelligent I/O interrupt control register 2 */
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#pragma ADDRESS tb3ic_addr 0078H /* Timer B3 interrupt control register */
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#pragma ADDRESS iio4ic_addr 0079H /* Intelligent I/O interrupt control register 4 */
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#pragma ADDRESS int5ic_addr 007aH /* INT5~ interrupt control register */
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#pragma ADDRESS iio6ic_addr 007bH /* Intelligent I/O interrupt control register 6 */
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#pragma ADDRESS int3ic_addr 007cH /* INT3~ interrupt control register */
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#pragma ADDRESS iio8ic_addr 007dH /* Intelligent I/O interrupt control register 8 */
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#pragma ADDRESS int1ic_addr 007eH /* INT1~ interrupt control register */
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#pragma ADDRESS iio10ic_addr 007fH /* Intelligent I/O interrupt control register 10 */
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#pragma ADDRESS can1ic_addr 007fH /* CAN1 Interrupt Control Register*/
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#pragma ADDRESS iio11ic_addr 0081H /* Intelligent I/O interrupt control register 11 */
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#pragma ADDRESS can2ic_addr 0081H /* CAN2 Interrupt Control Register*/
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#pragma ADDRESS ad1ic_addr 0086H /* A/D1 conversion interrupt control register */
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#pragma ADDRESS dm1ic_addr 0088H /* DMA1 interrupt control register */
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#pragma ADDRESS s2tic_addr 0089H /* UART2 transmit/nack interrupt control register */
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#pragma ADDRESS dm3ic_addr 008aH /* DMA3 interrupt control register */
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#pragma ADDRESS s3tic_addr 008bH /* UART3 transmit/nack interrupt control register */
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#pragma ADDRESS ta1ic_addr 008cH /* Timer A1 interrupt control register */
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#pragma ADDRESS s4tic_addr 008dH /* UART4 transmit/nack interrupt control register */
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#pragma ADDRESS ta3ic_addr 008eH /* Timer A3 interrupt control register */
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#pragma ADDRESS bcn2ic_addr 008fH /* Bus collision (UART2) interrupt control register */
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#pragma ADDRESS s0tic_addr 0090H /* UART0 transmit interrupt control register */
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#pragma ADDRESS bcn4ic_addr 0091H /* Bus collision (UART4) interrupt control register */
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#pragma ADDRESS bcn1ic_addr 0091H /* Bus collision (UART1) interrupt control register*/
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#pragma ADDRESS s1tic_addr 0092H /* UART1 transmit interrupt control register */
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#pragma ADDRESS kupic_addr 0093H /* Key input interrupt control register */
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#pragma ADDRESS tb0ic_addr 0094H /* Timer B0 interrupt control register */
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#pragma ADDRESS iio1ic_addr 0095H /* Intelligent I/O interrupt control register 1 */
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#pragma ADDRESS tb2ic_addr 0096H /* Timer B2 interrupt control register */
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#pragma ADDRESS iio3ic_addr 0097H /* Intelligent I/O interrupt control register 3 */
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#pragma ADDRESS tb4ic_addr 0098H /* Timer B4 interrupt control register */
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#pragma ADDRESS iio5ic_addr 0099H /* Intelligent I/O interrupt control register 5 */
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#pragma ADDRESS int4ic_addr 009aH /* INT4~ interrupt control register */
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#pragma ADDRESS iio7ic_addr 009bH /* Intelligent I/O interrupt control register 7 */
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#pragma ADDRESS int2ic_addr 009cH /* INT2~ interrupt control register */
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#pragma ADDRESS iio9ic_addr 009dH /* Intelligent I/O interrupt control register 9 */
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#pragma ADDRESS can0ic_addr 009dH /* CAN0 Interrupt Control Register*/
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#pragma ADDRESS int0ic_addr 009eH /* INT0~ interrupt control register */
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#pragma ADDRESS rlvl_addr 009fH /* Exit priority register */
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#pragma ADDRESS iio0ir_addr 00a0H /* Interrupt request register 0 */
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#pragma ADDRESS iio1ir_addr 00a1H /* Interrupt request register 1 */
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#pragma ADDRESS iio2ir_addr 00a2H /* Interrupt request register 2 */
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#pragma ADDRESS iio3ir_addr 00a3H /* Interrupt request register 3 */
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#pragma ADDRESS iio4ir_addr 00a4H /* Interrupt request register 4 */
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#pragma ADDRESS iio5ir_addr 00a5H /* Interrupt request register 5 */
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#pragma ADDRESS iio6ir_addr 00a6H /* Interrupt request register 6 */
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#pragma ADDRESS iio7ir_addr 00a7H /* Interrupt request register 7 */
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#pragma ADDRESS iio8ir_addr 00a8H /* Interrupt request register 8 */
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#pragma ADDRESS iio9ir_addr 00a9H /* Interrupt request register 9 */
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#pragma ADDRESS iio10ir_addr 00aaH /* Interrupt request register 10 */
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#pragma ADDRESS iio11ir_addr 00abH /* Interrupt request register 11 */
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#pragma ADDRESS iio0ie_addr 00b0H /* Interrupt enable register 0 */
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#pragma ADDRESS iio1ie_addr 00b1H /* Interrupt enable register 1 */
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#pragma ADDRESS iio2ie_addr 00b2H /* Interrupt enable register 2 */
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#pragma ADDRESS iio3ie_addr 00b3H /* Interrupt enable register 3 */
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#pragma ADDRESS iio4ie_addr 00b4H /* Interrupt enable register 4 */
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#pragma ADDRESS iio5ie_addr 00b5H /* Interrupt enable register 5 */
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#pragma ADDRESS iio6ie_addr 00b6H /* Interrupt enable register 6 */
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#pragma ADDRESS iio7ie_addr 00b7H /* Interrupt enable register 7 */
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#pragma ADDRESS iio8ie_addr 00b8H /* Interrupt enable register 8 */
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#pragma ADDRESS iio9ie_addr 00b9H /* Interrupt enable register 9 */
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#pragma ADDRESS iio10ie_addr 00baH /* Interrupt enable register 10 */
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#pragma ADDRESS iio11ie_addr 00bbH /* Interrupt enable register 11 */
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#pragma ADDRESS g0tm0_addr 00c0H /* Group 0 time measurement register 0 */
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#pragma ADDRESS g0tm1_addr 00c2H /* Group 0 time measurement register 1 */
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#pragma ADDRESS g0tm2_addr 00c4H /* Group 0 time measurement register 2 */
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#pragma ADDRESS g0tm3_addr 00c6H /* Group 0 time measurement register 3 */
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#pragma ADDRESS g0tm4_addr 00c8H /* Group 0 time measurement register 4 */
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#pragma ADDRESS g0tm5_addr 00caH /* Group 0 time measurement register 5 */
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#pragma ADDRESS g0tm6_addr 00ccH /* Group 0 time measurement register 6 */
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#pragma ADDRESS g0tm7_addr 00ceH /* Group 0 time measurement register 7 */
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#pragma ADDRESS g0po0_addr 00c0H /* Group 0 waveform generate register 0 */
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#pragma ADDRESS g0po1_addr 00c2H /* Group 0 waveform generate register 1 */
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#pragma ADDRESS g0po2_addr 00c4H /* Group 0 waveform generate register 2 */
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#pragma ADDRESS g0po3_addr 00c6H /* Group 0 waveform generate register 3 */
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#pragma ADDRESS g0po4_addr 00c8H /* Group 0 waveform generate register 4 */
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#pragma ADDRESS g0po5_addr 00caH /* Group 0 waveform generate register 5 */
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#pragma ADDRESS g0po6_addr 00ccH /* Group 0 waveform generate register 6 */
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#pragma ADDRESS g0po7_addr 00ceH /* Group 0 waveform generate register 7 */
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#pragma ADDRESS g0pocr0_addr 00d0H /* Group 0 pulse output control register0 */
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#pragma ADDRESS g0pocr1_addr 00d1H /* Group 0 pulse output control register1 */
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#pragma ADDRESS g0pocr2_addr 00d2H /* Group 0 pulse output control register2 */
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#pragma ADDRESS g0pocr3_addr 00d3H /* Group 0 pulse output control register3 */
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#pragma ADDRESS g0pocr4_addr 00d4H /* Group 0 pulse output control register4 */
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#pragma ADDRESS g0pocr5_addr 00d5H /* Group 0 pulse output control register5 */
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#pragma ADDRESS g0pocr6_addr 00d6H /* Group 0 pulse output control register6 */
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#pragma ADDRESS g0pocr7_addr 00d7H /* Group 0 pulse output control register7 */
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#pragma ADDRESS g0tmcr0_addr 00d8H /* Group 0 time measuring control register0 */
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#pragma ADDRESS g0tmcr1_addr 00d9H /* Group 0 time measuring control register1 */
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#pragma ADDRESS g0tmcr2_addr 00daH /* Group 0 time measuring control register2 */
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#pragma ADDRESS g0tmcr3_addr 00dbH /* Group 0 time measuring control register3 */
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#pragma ADDRESS g0tmcr4_addr 00dcH /* Group 0 time measuring control register4 */
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#pragma ADDRESS g0tmcr5_addr 00ddH /* Group 0 time measuring control register5 */
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#pragma ADDRESS g0tmcr6_addr 00deH /* Group 0 time measuring control register6 */
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#pragma ADDRESS g0tmcr7_addr 00dfH /* Group 0 time measuring control register7 */
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#pragma ADDRESS g0bt_addr 00e0H /* Group 0 base timer register */
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#pragma ADDRESS g0bcr0_addr 00e2H /* Group 0 base timer control register0 */
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#pragma ADDRESS g0bcr1_addr 00e3H /* Group 0 base timer control register1 */
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#pragma ADDRESS g0tpr6_addr 00e4H /* Group 0 priscale reload register6 */
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#pragma ADDRESS g0tpr7_addr 00e5H /* Group 0 priscale reload register7 */
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#pragma ADDRESS g0fe_addr 00e6H /* Group 0 function enable register */
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#pragma ADDRESS g0fs_addr 00e7H /* Group 0 function select register */
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#pragma ADDRESS g0rb_addr 00e8H /* Group 0 SI/O receive buffer register */
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#pragma ADDRESS g0tb_addr 00eaH /* Group 0 SI/O transmitting buffer register */
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#pragma ADDRESS g0dr_addr 00eaH /* Group 0 receive data register */
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#pragma ADDRESS g0ri_addr 00ecH /* Group 0 receive input register */
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#pragma ADDRESS g0mr_addr 00edH /* Group 0 SI/O communication control register */
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#pragma ADDRESS g0to_addr 00eeH /* Group 0 transmit output register */
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#pragma ADDRESS g0cr_addr 00efH /* Group 0 SI/O communication control register */
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#pragma ADDRESS g0cmp0_addr 00f0H /* Group 0 data compare register 0 */
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#pragma ADDRESS g0cmp1_addr 00f1H /* Group 0 data compare register 1 */
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#pragma ADDRESS g0cmp2_addr 00f2H /* Group 0 data compare register 2 */
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#pragma ADDRESS g0cmp3_addr 00f3H /* Group 0 data compare register 3 */
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#pragma ADDRESS g0msk0_addr 00f4H /* Group 0 data mask register 0 */
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#pragma ADDRESS g0msk1_addr 00f5H /* Group 0 data mask register 1 */
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#pragma ADDRESS g0rcrc_addr 00f8H /* Group 0 receive CRC code register */
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#pragma ADDRESS g0tcrc_addr 00faH /* Group 0 transmit CRC code register */
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#pragma ADDRESS g0emr_addr 00fcH /* Group 0 SI/O expansion mode register */
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#pragma ADDRESS g0erc_addr 00fdH /* Group 0 SI/O expansion receive control register */
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#pragma ADDRESS g0irf_addr 00feH /* Group 0 SI/O special communication interrupt detect register */
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#pragma ADDRESS g0etc_addr 00ffH /* Group 0 SI/O expansion transmit control register */
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#pragma ADDRESS g1tm0_addr 0100H /* Group 1 time measurement register 0 */
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#pragma ADDRESS g1po0_addr 0100H /* Group 1 waveform generate register 0 */
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#pragma ADDRESS g1tm1_addr 0102H /* Group 1 time measurement register 1 */
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#pragma ADDRESS g1po1_addr 0102H /* Group 1 waveform generate register 1 */
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#pragma ADDRESS g1tm2_addr 0104H /* Group 1 time measurement register 2 */
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#pragma ADDRESS g1po2_addr 0104H /* Group 1 waveform generate register 2 */
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#pragma ADDRESS g1tm3_addr 0106H /* Group 1 time measurement register 3 */
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#pragma ADDRESS g1po3_addr 0106H /* Group 1 waveform generate register 3 */
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#pragma ADDRESS g1tm4_addr 0108H /* Group 1 time measurement register 4 */
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#pragma ADDRESS g1po4_addr 0108H /* Group 1 waveform generate register 4 */
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#pragma ADDRESS g1tm5_addr 010aH /* Group 1 time measurement register 5 */
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#pragma ADDRESS g1po5_addr 010aH /* Group 1 waveform generate register 5 */
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#pragma ADDRESS g1tm6_addr 010cH /* Group 1 time measurement register 6 */
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#pragma ADDRESS g1po6_addr 010cH /* Group 1 waveform generate register 6 */
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#pragma ADDRESS g1tm7_addr 010eH /* Group 1 time measurement register 7 */
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#pragma ADDRESS g1po7_addr 010eH /* Group 1 waveform generate register 7 */
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#pragma ADDRESS g1pocr0_addr 0110H /* Group 1 waveform generate control register 0 */
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#pragma ADDRESS g1pocr1_addr 0111H /* Group 1 waveform generate control register 1 */
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#pragma ADDRESS g1pocr2_addr 0112H /* Group 1 waveform generate control register 2 */
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#pragma ADDRESS g1pocr3_addr 0113H /* Group 1 waveform generate control register 3 */
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#pragma ADDRESS g1pocr4_addr 0114H /* Group 1 waveform generate control register 4 */
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#pragma ADDRESS g1pocr5_addr 0115H /* Group 1 waveform generate control register 5 */
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#pragma ADDRESS g1pocr6_addr 0116H /* Group 1 waveform generate control register 6 */
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#pragma ADDRESS g1pocr7_addr 0117H /* Group 1 waveform generate control register 7 */
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#pragma ADDRESS g1tmcr0_addr 0118H /* Group 1 time measurement control register 0 */
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#pragma ADDRESS g1tmcr1_addr 0119H /* Group 1 time measurement control register 1 */
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#pragma ADDRESS g1tmcr2_addr 011aH /* Group 1 time measurement control register 2 */
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#pragma ADDRESS g1tmcr3_addr 011bH /* Group 1 time measurement control register 3 */
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#pragma ADDRESS g1tmcr4_addr 011cH /* Group 1 time measurement control register 4 */
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#pragma ADDRESS g1tmcr5_addr 011dH /* Group 1 time measurement control register 5 */
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#pragma ADDRESS g1tmcr6_addr 011eH /* Group 1 time measurement control register 6 */
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#pragma ADDRESS g1tmcr7_addr 011fH /* Group 1 time measurement control register 7 */
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#pragma ADDRESS g1bt_addr 0120H /* Group 1 base timer register */
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#pragma ADDRESS g1bcr0_addr 0122H /* Group 1 base timer control register 0 */
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#pragma ADDRESS g1bcr1_addr 0123H /* Group 1 base timer control register 1 */
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#pragma ADDRESS g1tpr6_addr 0124H /* Group 1 time measurement prescaler register 6 */
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#pragma ADDRESS g1tpr7_addr 0125H /* Group 1 time measurement prescaler register 7 */
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#pragma ADDRESS g1fe_addr 0126H /* Group 1 function enable register */
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#pragma ADDRESS g1fs_addr 0127H /* Group 1 function select register */
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#pragma ADDRESS g1rb_addr 0128H /* Group 1 SI/O communication buffer register */
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#pragma ADDRESS g1tb_addr 012aH /* Group 1 SI/O transmiting data register */
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#pragma ADDRESS g1dr_addr 012aH /* Group 1 receive data register */
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#pragma ADDRESS g1ri_addr 012cH /* Group 1 receive input register */
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#pragma ADDRESS g1mr_addr 012dH /* Group 1 SI/O communication mode register */
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#pragma ADDRESS g1to_addr 012eH /* Group 1 transmit output register */
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#pragma ADDRESS g1cr_addr 012fH /* Group 1 SI/O communication control register */
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#pragma ADDRESS g1cmp0_addr 0130H /* Group 1 data compare register 0 */
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||
|
#pragma ADDRESS g1cmp1_addr 0131H /* Group 1 data compare register 1 */
|
||
|
#pragma ADDRESS g1cmp2_addr 0132H /* Group 1 data compare register 2 */
|
||
|
#pragma ADDRESS g1cmp3_addr 0133H /* Group 1 data compare register 3 */
|
||
|
#pragma ADDRESS g1msk0_addr 0134H /* Group 1 data mask register 0 */
|
||
|
#pragma ADDRESS g1msk1_addr 0135H /* Group 1 data mask register 1 */
|
||
|
#pragma ADDRESS g1rcrc_addr 0138H /* Group 1 receive CRC code register */
|
||
|
#pragma ADDRESS g1tcrc_addr 013aH /* Group 1 transmit CRC code register */
|
||
|
#pragma ADDRESS g1emr_addr 013cH /* Group 1 SI/O expansion mode register */
|
||
|
#pragma ADDRESS g1erc_addr 013dH /* Group 1 SI/O expansion receive control register */
|
||
|
#pragma ADDRESS g1irf_addr 013eH /* Group 1 SI/O special communication interrupt detect register */
|
||
|
#pragma ADDRESS g1etc_addr 013fH /* Group 1 SI/O expansion transmit control register */
|
||
|
#pragma ADDRESS g2po0_addr 0140H /* Group 2 waveform generate register 0 */
|
||
|
#pragma ADDRESS g2po1_addr 0142H /* Group 2 waveform generate register 1 */
|
||
|
#pragma ADDRESS g2po2_addr 0144H /* Group 2 waveform generate register 2 */
|
||
|
#pragma ADDRESS g2po3_addr 0146H /* Group 2 waveform generate register 3 */
|
||
|
#pragma ADDRESS g2po4_addr 0148H /* Group 2 waveform generate register 4 */
|
||
|
#pragma ADDRESS g2po5_addr 014aH /* Group 2 waveform generate register 5 */
|
||
|
#pragma ADDRESS g2po6_addr 014cH /* Group 2 waveform generate register 6 */
|
||
|
#pragma ADDRESS g2po7_addr 014eH /* Group 2 waveform generate register 7 */
|
||
|
#pragma ADDRESS g2pocr0_addr 0150H /* Group 2 waveform generate control register 0 */
|
||
|
#pragma ADDRESS g2pocr1_addr 0151H /* Group 2 waveform generate control register 1 */
|
||
|
#pragma ADDRESS g2pocr2_addr 0152H /* Group 2 waveform generate control register 2 */
|
||
|
#pragma ADDRESS g2pocr3_addr 0153H /* Group 2 waveform generate control register 3 */
|
||
|
#pragma ADDRESS g2pocr4_addr 0154H /* Group 2 waveform generate control register 4 */
|
||
|
#pragma ADDRESS g2pocr5_addr 0155H /* Group 2 waveform generate control register 5 */
|
||
|
#pragma ADDRESS g2pocr6_addr 0156H /* Group 2 waveform generate control register 6 */
|
||
|
#pragma ADDRESS g2pocr7_addr 0157H /* Group 2 waveform generate control register 7 */
|
||
|
#pragma ADDRESS g2bt_addr 0160H /* Group 2 base timer register */
|
||
|
#pragma ADDRESS g2bcr0_addr 0162H /* Group 2 base timer control register 0 */
|
||
|
#pragma ADDRESS g2bcr1_addr 0163H /* Group 2 base timer control register 1 */
|
||
|
#pragma ADDRESS btsr_addr 0164H /* base timer start register */
|
||
|
#pragma ADDRESS g2fe_addr 0166H /* Group 2 function enable register */
|
||
|
#pragma ADDRESS g2rtp_addr 0167H /* Group 2 RTP output buffer register */
|
||
|
#pragma ADDRESS g2mr_addr 016aH /* Group 2 SI/O communication mode register */
|
||
|
#pragma ADDRESS g2cr_addr 016bH /* Group 2 SI/O communication control register */
|
||
|
#pragma ADDRESS g2tb_addr 016cH /* Group 2 SI/O transmit buffer register */
|
||
|
#pragma ADDRESS g2rb_addr 016eH /* Group 2 SI/O receive buffer register */
|
||
|
#pragma ADDRESS iear_addr 0170H /* Group 2 IEBus address register */
|
||
|
#pragma ADDRESS iecr_addr 0172H /* Group 2 IEBus control register */
|
||
|
#pragma ADDRESS ietif_addr 0173H /* Group 2 IEBus transmit interrupt cause detect register */
|
||
|
#pragma ADDRESS ierif_addr 0174H /* Group 2 IEBus receive interrupt cause detect register */
|
||
|
#pragma ADDRESS ips_addr 0178H /* Input function select register */
|
||
|
#pragma ADDRESS g3mr_addr 017aH /* Group 3 SI/O communication mode register */
|
||
|
#pragma ADDRESS g3cr_addr 017bH /* Group 3 SI/O communication control register */
|
||
|
#pragma ADDRESS g3tb_addr 017cH /* Group 3 SI/O transmit buffer register */
|
||
|
#pragma ADDRESS g3rb_addr 017eH /* Group 3 SI/O receive buffer register */
|
||
|
#pragma ADDRESS g3po0_addr 0180H /* Group 3 waveform generate register 0 */
|
||
|
#pragma ADDRESS g3po1_addr 0182H /* Group 3 waveform generate register 1 */
|
||
|
#pragma ADDRESS g3po2_addr 0184H /* Group 3 waveform generate register 2 */
|
||
|
#pragma ADDRESS g3po3_addr 0186H /* Group 3 waveform generate register 3 */
|
||
|
#pragma ADDRESS g3po4_addr 0188H /* Group 3 waveform generate register 4 */
|
||
|
#pragma ADDRESS g3po5_addr 018aH /* Group 3 waveform generate register 5 */
|
||
|
#pragma ADDRESS g3po6_addr 018cH /* Group 3 waveform generate register 6 */
|
||
|
#pragma ADDRESS g3po7_addr 018eH /* Group 3 waveform generate register 7 */
|
||
|
#pragma ADDRESS g3pocr0_addr 0190H /* Group 3 waveform generate control register 0 */
|
||
|
#pragma ADDRESS g3pocr1_addr 0191H /* Group 3 waveform generate control register 1 */
|
||
|
#pragma ADDRESS g3pocr2_addr 0192H /* Group 3 waveform generate control register 2 */
|
||
|
#pragma ADDRESS g3pocr3_addr 0193H /* Group 3 waveform generate control register 3 */
|
||
|
#pragma ADDRESS g3pocr4_addr 0194H /* Group 3 waveform generate control register 4 */
|
||
|
#pragma ADDRESS g3pocr5_addr 0195H /* Group 3 waveform generate control register 5 */
|
||
|
#pragma ADDRESS g3pocr6_addr 0196H /* Group 3 waveform generate control register 6 */
|
||
|
#pragma ADDRESS g3pocr7_addr 0197H /* Group 3 waveform generate control register 7 */
|
||
|
#pragma ADDRESS g3mk4_addr 0198H /* Group 3 waveform generate mask register 4 */
|
||
|
#pragma ADDRESS g3mk5_addr 019aH /* Group 3 waveform generate mask register 5 */
|
||
|
#pragma ADDRESS g3mk6_addr 019cH /* Group 3 waveform generate mask register 6 */
|
||
|
#pragma ADDRESS g3mk7_addr 019eH /* Group 3 waveform generate mask register 7 */
|
||
|
#pragma ADDRESS g3bt_addr 01a0H /* Group 3 base timer register */
|
||
|
#pragma ADDRESS g3bcr0_addr 01a2H /* Group 3 base timer control register 0 */
|
||
|
#pragma ADDRESS g3bcr1_addr 01a3H /* Group 3 base timer control register 1 */
|
||
|
#pragma ADDRESS g3fe_addr 01a6H /* Group 3 function enable register */
|
||
|
#pragma ADDRESS g3rtp_addr 01a7H /* Group 3 RTP output buffer register */
|
||
|
//#pragma ADDRESS hdlc1_addr 01abH /* Group 3 high-speed HDLC Communication Control Register 1 */
|
||
|
#pragma ADDRESS hdlc_addr 01acH /* Group 3 high-speed HDLC communication control register */
|
||
|
#pragma ADDRESS g3flg_addr 01adH /* Group 3 high-speed HDLC communication register */
|
||
|
#pragma ADDRESS hcnt_addr 01aeH /* Group 3 high-speed HDLC transmit counter */
|
||
|
#pragma ADDRESS hadr0_addr 01b0H /* Group 3 high-speed HDLC data compare register 0 */
|
||
|
#pragma ADDRESS hmsk0_addr 01b2H /* Group 3 high-speed HDLC data mask register 0 */
|
||
|
#pragma ADDRESS hadr1_addr 01b4H /* Group 3 high-speed HDLC data compare register 1 */
|
||
|
#pragma ADDRESS hmsk1_addr 01b6H /* Group 3 high-speed HDLC data mask register 1 */
|
||
|
#pragma ADDRESS hadr2_addr 01b8H /* Group 3 high-speed HDLC data compare register 2 */
|
||
|
#pragma ADDRESS hmsk2_addr 01baH /* Group 3 high-speed HDLC data mask register 2 */
|
||
|
#pragma ADDRESS hadr3_addr 01bcH /* Group 3 high-speed HDLC data compare register 3 */
|
||
|
#pragma ADDRESS hmsk3_addr 01beH /* Group 3 high-speed HDLC data mask register 3 */
|
||
|
|
||
|
#pragma ADDRESS ad10_addr 01c0H /* A/D1 register 0 */
|
||
|
#pragma ADDRESS ad11_addr 01c2H /* A/D1 register 1 */
|
||
|
#pragma ADDRESS ad12_addr 01c4H /* A/D1 register 2 */
|
||
|
#pragma ADDRESS ad13_addr 01c6H /* A/D1 register 3 */
|
||
|
#pragma ADDRESS ad14_addr 01c8H /* A/D1 register 4 */
|
||
|
#pragma ADDRESS ad15_addr 01caH /* A/D1 register 5 */
|
||
|
#pragma ADDRESS ad16_addr 01ccH /* A/D1 register 6 */
|
||
|
#pragma ADDRESS ad17_addr 01ceH /* A/D1 register 7 */
|
||
|
#pragma ADDRESS ad1con2_addr 01d4H /* A/D1 control register 2 */
|
||
|
#pragma ADDRESS ad1con0_addr 01d6H /* A/D1 control register 0 */
|
||
|
#pragma ADDRESS ad1con1_addr 01d7H /* A/D1 control register 1 */
|
||
|
|
||
|
#pragma ADDRESS c0slot0_0_addr 01e0H /* Can0 Messege Slot Buffer0 Data0 */
|
||
|
#pragma ADDRESS c0slot0_1_addr 01e1H /* Can0 Messege Slot Buffer0 Data1 */
|
||
|
#pragma ADDRESS c0slot0_2_addr 01e2H /* Can0 Messege Slot Buffer0 Data2 */
|
||
|
#pragma ADDRESS c0slot0_3_addr 01e3H /* Can0 Messege Slot Buffer0 Data3 */
|
||
|
#pragma ADDRESS c0slot0_4_addr 01e4H /* Can0 Messege Slot Buffer0 Data4 */
|
||
|
#pragma ADDRESS c0slot0_5_addr 01e5H /* Can0 Messege Slot Buffer0 Data5 */
|
||
|
#pragma ADDRESS c0slot0_6_addr 01e6H /* Can0 Messege Slot Buffer0 Data6 */
|
||
|
#pragma ADDRESS c0slot0_7_addr 01e7H /* Can0 Messege Slot Buffer0 Data7 */
|
||
|
#pragma ADDRESS c0slot0_8_addr 01e8H /* Can0 Messege Slot Buffer0 Data8 */
|
||
|
#pragma ADDRESS c0slot0_9_addr 01e9H /* Can0 Messege Slot Buffer0 Data9 */
|
||
|
#pragma ADDRESS c0slot0_10_addr 01eaH /* Can0 Messege Slot Buffer0 Data10 */
|
||
|
#pragma ADDRESS c0slot0_11_addr 01ebH /* Can0 Messege Slot Buffer0 Data11 */
|
||
|
#pragma ADDRESS c0slot0_12_addr 01ecH /* Can0 Messege Slot Buffer0 Data12 */
|
||
|
#pragma ADDRESS c0slot0_13_addr 01edH /* Can0 Messege Slot Buffer0 Data13 */
|
||
|
#pragma ADDRESS c0slot0_14_addr 01eeH /* Can0 Messege Slot Buffer0 Data14 */
|
||
|
#pragma ADDRESS c0slot0_15_addr 01efH /* Can0 Messege Slot Buffer0 Data15 */
|
||
|
#pragma ADDRESS c0slot1_0_addr 01f0H /* Can0 Messege Slot Buffer1 Data0 */
|
||
|
#pragma ADDRESS c0slot1_1_addr 01f1H /* Can0 Messege Slot Buffer1 Data1 */
|
||
|
#pragma ADDRESS c0slot1_2_addr 01f2H /* Can0 Messege Slot Buffer1 Data2 */
|
||
|
#pragma ADDRESS c0slot1_3_addr 01f3H /* Can0 Messege Slot Buffer1 Data3 */
|
||
|
#pragma ADDRESS c0slot1_4_addr 01f4H /* Can0 Messege Slot Buffer1 Data4 */
|
||
|
#pragma ADDRESS c0slot1_5_addr 01f5H /* Can0 Messege Slot Buffer1 Data5 */
|
||
|
#pragma ADDRESS c0slot1_6_addr 01f6H /* Can0 Messege Slot Buffer1 Data6 */
|
||
|
#pragma ADDRESS c0slot1_7_addr 01f7H /* Can0 Messege Slot Buffer1 Data7 */
|
||
|
#pragma ADDRESS c0slot1_8_addr 01f8H /* Can0 Messege Slot Buffer1 Data8 */
|
||
|
#pragma ADDRESS c0slot1_9_addr 01f9H /* Can0 Messege Slot Buffer1 Data9 */
|
||
|
#pragma ADDRESS c0slot1_10_addr 01faH /* Can0 Messege Slot Buffer1 Data10 */
|
||
|
#pragma ADDRESS c0slot1_11_addr 01fbH /* Can0 Messege Slot Buffer1 Data11 */
|
||
|
#pragma ADDRESS c0slot1_12_addr 01fcH /* Can0 Messege Slot Buffer1 Data12 */
|
||
|
#pragma ADDRESS c0slot1_13_addr 01fdH /* Can0 Messege Slot Buffer1 Data13 */
|
||
|
#pragma ADDRESS c0slot1_14_addr 01feH /* Can0 Messege Slot Buffer1 Data14 */
|
||
|
#pragma ADDRESS c0slot1_15_addr 01ffH /* Can0 Messege Slot Buffer1 Data15 */
|
||
|
#pragma ADDRESS c0ctlr0_addr 0200H /* Can0 Status Register */
|
||
|
#pragma ADDRESS c0str_addr 0202H /* Can0 Status Register */
|
||
|
#pragma ADDRESS c0idr_addr 0204H /* Can0 Extended ID Register */
|
||
|
#pragma ADDRESS c0conr_addr 0206H /* Can0 Configration Register */
|
||
|
#pragma ADDRESS c0tsr_addr 0208H /* Can0 Time Stamp Register */
|
||
|
#pragma ADDRESS c0tec_addr 020aH /* Can0 Transmit Error Count Register */
|
||
|
#pragma ADDRESS c0rec_addr 020bH /* Can0 Receive Error Count Register */
|
||
|
#pragma ADDRESS c0sistr_addr 020cH /* Can0 Slot Interrupt Status Register */
|
||
|
#pragma ADDRESS c0simkr_addr 0210H /* Can0 Slot Interrupt Mask Register */
|
||
|
#pragma ADDRESS c0eimkr_addr 0214H /* Can0 Error Interrupt Mask Register */
|
||
|
#pragma ADDRESS c0eistr_addr 0215H /* Can0 Error Interrupt Status Register */
|
||
|
#pragma ADDRESS c0brp_addr 0217H /* Can0 Baud Rate Prescaler */
|
||
|
#pragma ADDRESS c0gmr0_addr 0228H /* Can0 Global Mask Register Standard ID0 */
|
||
|
#pragma ADDRESS c0gmr1_addr 0229H /* Can0 Global Mask Register Standard ID1 */
|
||
|
#pragma ADDRESS c0gmr2_addr 022aH /* Can0 Global Mask Register Extended ID0 */
|
||
|
#pragma ADDRESS c0gmr3_addr 022bH /* Can0 Global Mask Register Extended ID1 */
|
||
|
#pragma ADDRESS c0gmr4_addr 022cH /* Can0 Global Mask Register Extended ID2 */
|
||
|
#pragma ADDRESS c0mctl0_addr 0230H /* Can0 Messege Slot0 Control Register */
|
||
|
#pragma ADDRESS c0lmar0_addr 0230H /* Can0 Local Mask RegisterA Standard ID0 */
|
||
|
#pragma ADDRESS c0mctl1_addr 0231H /* Can0 Messege Slot1 Control Register */
|
||
|
#pragma ADDRESS c0lmar1_addr 0231H /* Can0 Local Mask RegisterA Standard ID1 */
|
||
|
#pragma ADDRESS c0mctl2_addr 0232H /* Can0 Messege Slot2 Control Register */
|
||
|
#pragma ADDRESS c0lmar2_addr 0232H /* Can0 Local Mask RegisterA Extended ID0 */
|
||
|
#pragma ADDRESS c0mctl3_addr 0233H /* Can0 Messege Slot3 Control Register */
|
||
|
#pragma ADDRESS c0lmar3_addr 0233H /* Can0 Local Mask RegisterA Extended ID1 */
|
||
|
#pragma ADDRESS c0mctl4_addr 0234H /* Can0 Messege Slot4 Control Register */
|
||
|
#pragma ADDRESS c0lmar4_addr 0234H /* Can0 Local Mask RegisterA Extended ID2 */
|
||
|
#pragma ADDRESS c0mctl5_addr 0235H /* Can0 Messege Slot5 Control Register */
|
||
|
#pragma ADDRESS c0mctl6_addr 0236H /* Can0 Messege Slot6 Control Register */
|
||
|
#pragma ADDRESS c0mctl7_addr 0237H /* Can0 Messege Slot7 Control Register */
|
||
|
#pragma ADDRESS c0mctl8_addr 0238H /* Can0 Messege Slot8 Control Register */
|
||
|
#pragma ADDRESS c0lmbr0_addr 0238H /* Can0 Local Mask RegisterB Standard ID0 */
|
||
|
#pragma ADDRESS c0mctl9_addr 0239H /* Can0 Messege Slot9 Control Register */
|
||
|
#pragma ADDRESS c0lmbr1_addr 0239H /* Can0 Local Mask RegisterB Standard ID1 */
|
||
|
#pragma ADDRESS c0mctl10_addr 023aH /* Can0 Messege Slot10 Control Register */
|
||
|
#pragma ADDRESS c0lmbr2_addr 023aH /* Can0 Local Mask RegisterB Extended ID2 */
|
||
|
#pragma ADDRESS c0mctl11_addr 023bH /* Can0 Messege Slot11 Control Register */
|
||
|
#pragma ADDRESS c0lmbr3_addr 023bH /* Can0 Local Mask RegisterB Extended ID3 */
|
||
|
#pragma ADDRESS c0mctl12_addr 023cH /* Can0 Messege Slot12 Control Register */
|
||
|
#pragma ADDRESS c0lmbr4_addr 023cH /* Can0 Local Mask RegisterB Extended ID4 */
|
||
|
#pragma ADDRESS c0mctl13_addr 023dH /* Can0 Messege Slot13 Control Register */
|
||
|
#pragma ADDRESS c0mctl14_addr 023eH /* Can0 Messege Slot14 Control Register */
|
||
|
#pragma ADDRESS c0mctl15_addr 023fH /* Can0 Messege Slot15 Control Register */
|
||
|
#pragma ADDRESS c0sbs_addr 0240H /* Can0 Slot Buffer Select Register */
|
||
|
#pragma ADDRESS c0ctlr1_addr 0241H /* Can0 Control Register 1 */
|
||
|
#pragma ADDRESS c0slpr_addr 0242H /* Can0 Clock Stop Control Register */
|
||
|
#pragma ADDRESS c0afs_addr 0244H /* Can0 Acceptance Filtering Support Unit */
|
||
|
|
||
|
#pragma ADDRESS x0r_addr 02c0H /* X0 register */
|
||
|
#pragma ADDRESS y0r_addr 02c0H /* Y0 register */
|
||
|
#pragma ADDRESS x1r_addr 02c2H /* X1 register */
|
||
|
#pragma ADDRESS y1r_addr 02c2H /* Y1 register */
|
||
|
#pragma ADDRESS x2r_addr 02c4H /* X2 register */
|
||
|
#pragma ADDRESS y2r_addr 02c4H /* Y2 register */
|
||
|
#pragma ADDRESS x3r_addr 02c6H /* X3 register */
|
||
|
#pragma ADDRESS y3r_addr 02c6H /* Y3 register */
|
||
|
#pragma ADDRESS x4r_addr 02c8H /* X4 register */
|
||
|
#pragma ADDRESS y4r_addr 02c8H /* Y4 register */
|
||
|
#pragma ADDRESS x5r_addr 02caH /* X5 register */
|
||
|
#pragma ADDRESS y5r_addr 02caH /* Y5 register */
|
||
|
#pragma ADDRESS x6r_addr 02ccH /* X6 register */
|
||
|
#pragma ADDRESS y6r_addr 02ccH /* Y6 register */
|
||
|
#pragma ADDRESS x7r_addr 02ceH /* X7 register */
|
||
|
#pragma ADDRESS y7r_addr 02ceH /* Y7 register */
|
||
|
#pragma ADDRESS x8r_addr 02d0H /* X8 register */
|
||
|
#pragma ADDRESS y8r_addr 02d0H /* Y8 register */
|
||
|
#pragma ADDRESS x9r_addr 02d2H /* X9 register */
|
||
|
#pragma ADDRESS y9r_addr 02d2H /* Y9 register */
|
||
|
#pragma ADDRESS x10r_addr 02d4H /* X10 register */
|
||
|
#pragma ADDRESS y10r_addr 02d4H /* Y10 register */
|
||
|
#pragma ADDRESS x11r_addr 02d6H /* X11 register */
|
||
|
#pragma ADDRESS y11r_addr 02d6H /* Y11 register */
|
||
|
#pragma ADDRESS x12r_addr 02d8H /* X12 register */
|
||
|
#pragma ADDRESS y12r_addr 02d8H /* Y12 register */
|
||
|
#pragma ADDRESS x13r_addr 02daH /* X13 register */
|
||
|
#pragma ADDRESS y13r_addr 02daH /* Y13 register */
|
||
|
#pragma ADDRESS x14r_addr 02dcH /* X14 register */
|
||
|
#pragma ADDRESS y14r_addr 02dcH /* Y14 register */
|
||
|
#pragma ADDRESS x15r_addr 02deH /* X15 register */
|
||
|
#pragma ADDRESS y15r_addr 02deH /* Y15 register */
|
||
|
#pragma ADDRESS xyc_addr 02e0H /* X-Y control register */
|
||
|
|
||
|
#pragma ADDRESS u1smr4_addr 02e4H /* UART1 special mode register 4 */
|
||
|
#pragma ADDRESS u1smr3_addr 02e5H /* UART1 special mode register 3 */
|
||
|
#pragma ADDRESS u1smr2_addr 02e6H /* UART1 special mode register 2 */
|
||
|
#pragma ADDRESS u1smr_addr 02e7H /* UART1 special mode register */
|
||
|
#pragma ADDRESS u1mr_addr 02e8H /* UART1 transmit/receive mode register */
|
||
|
#pragma ADDRESS u1brg_addr 02e9H /* UART1 bit rate generator */
|
||
|
#pragma ADDRESS u1tb_addr 02eaH /* UART1 transmit buffer register */
|
||
|
#pragma ADDRESS u1c0_addr 02ecH /* UART1 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u1c1_addr 02edH /* UART1 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u1rb_addr 02eeH /* UART1 receive buffer register */
|
||
|
|
||
|
#pragma ADDRESS u4smr4_addr 02f4H /* UART4 special mode register 4 */
|
||
|
#pragma ADDRESS u4smr3_addr 02f5H /* UART4 special mode register 3 */
|
||
|
#pragma ADDRESS u4smr2_addr 02f6H /* UART4 special mode register 2 */
|
||
|
#pragma ADDRESS u4smr_addr 02f7H /* UART4 special mode register */
|
||
|
#pragma ADDRESS u4mr_addr 02f8H /* UART4 transmit/receive mode register */
|
||
|
#pragma ADDRESS u4brg_addr 02f9H /* UART4 bit rate generator */
|
||
|
#pragma ADDRESS u4tb_addr 02faH /* UART4 transmit buffer register */
|
||
|
#pragma ADDRESS u4c0_addr 02fcH /* UART4 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u4c1_addr 02fdH /* UART4 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u4rb_addr 02feH /* UART4 receive buffer register */
|
||
|
|
||
|
#pragma ADDRESS tbsr_addr 0300H /* Timer B3,4,5 count start flag */
|
||
|
#pragma ADDRESS ta11_addr 0302H /* Timer A1-1 register */
|
||
|
#pragma ADDRESS ta21_addr 0304H /* Timer A2-1 register */
|
||
|
#pragma ADDRESS ta41_addr 0306H /* Timer A4-1 register */
|
||
|
#pragma ADDRESS invc0_addr 0308H /* Three-phase PWM control regester 0 */
|
||
|
#pragma ADDRESS invc1_addr 0309H /* Three-phase PWM control register 1 */
|
||
|
#pragma ADDRESS idb0_addr 030aH /* Three-phase output buffer register 0 */
|
||
|
#pragma ADDRESS idb1_addr 030bH /* Three-phase output buffer register 1 */
|
||
|
#pragma ADDRESS dtt_addr 030cH /* Dead time timer */
|
||
|
#pragma ADDRESS ictb2_addr 030dH /* Timer B2 interrupt occurences frequency set counter */
|
||
|
#pragma ADDRESS tb3_addr 0310H /* Timer B3 register */
|
||
|
#pragma ADDRESS tb4_addr 0312H /* Timer B4 register */
|
||
|
#pragma ADDRESS tb5_addr 0314H /* Timer B5 register */
|
||
|
#pragma ADDRESS tb3mr_addr 031bH /* Timer B3 mode register */
|
||
|
#pragma ADDRESS tb4mr_addr 031cH /* Timer B4 mode register */
|
||
|
#pragma ADDRESS tb5mr_addr 031dH /* Timer B5 mode register */
|
||
|
#pragma ADDRESS ifsr_addr 031fH /* Interrupt cause select register */
|
||
|
|
||
|
#pragma ADDRESS u3smr4_addr 0324H /* UART3 special mode register 4 */
|
||
|
#pragma ADDRESS u3smr3_addr 0325H /* UART3 special mode register 3 */
|
||
|
#pragma ADDRESS u3smr2_addr 0326H /* UART3 special mode register 2 */
|
||
|
#pragma ADDRESS u3smr_addr 0327H /* UART3 special mode register */
|
||
|
#pragma ADDRESS u3mr_addr 0328H /* UART3 transmit/receive mode register */
|
||
|
#pragma ADDRESS u3brg_addr 0329H /* UART3 bit rate generator */
|
||
|
#pragma ADDRESS u3tb_addr 032aH /* UART3 transmit buffer register */
|
||
|
#pragma ADDRESS u3c0_addr 032cH /* UART3 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u3c1_addr 032dH /* UART3 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u3rb_addr 032eH /* UART3 receive buffer register */
|
||
|
#pragma ADDRESS u2smr4_addr 0334H /* UART2 special mode register 4 */
|
||
|
#pragma ADDRESS u2smr3_addr 0335H /* UART2 special mode register 3 */
|
||
|
#pragma ADDRESS u2smr2_addr 0336H /* UART2 special mode register 2 */
|
||
|
#pragma ADDRESS u2smr_addr 0337H /* UART2 special mode register */
|
||
|
#pragma ADDRESS u2mr_addr 0338H /* UART2 transmit/receive mode register */
|
||
|
#pragma ADDRESS u2brg_addr 0339H /* UART2 bit rate generator */
|
||
|
#pragma ADDRESS u2tb_addr 033aH /* UART2 transmit buffer register */
|
||
|
#pragma ADDRESS u2c0_addr 033cH /* UART2 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u2c1_addr 033dH /* UART2 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u2rb_addr 033eH /* UART2 receive buffer register */
|
||
|
|
||
|
#pragma ADDRESS tabsr_addr 0340H /* Count start flag */
|
||
|
#pragma ADDRESS cpsrf_addr 0341H /* Clock prescaler reset flag */
|
||
|
#pragma ADDRESS onsf_addr 0342H /* One-shot start flag */
|
||
|
#pragma ADDRESS trgsr_addr 0343H /* Trigger select register */
|
||
|
#pragma ADDRESS udf_addr 0344H /* Up/down flag */
|
||
|
#pragma ADDRESS ta0_addr 0346H /* Timer A0 register */
|
||
|
#pragma ADDRESS ta1_addr 0348H /* Timer A1 register */
|
||
|
#pragma ADDRESS ta2_addr 034aH /* Timer A2 register */
|
||
|
#pragma ADDRESS ta3_addr 034cH /* Timer A3 register */
|
||
|
#pragma ADDRESS ta4_addr 034eH /* Timer A4 register */
|
||
|
#pragma ADDRESS tb0_addr 0350H /* Timer B0 register */
|
||
|
#pragma ADDRESS tb1_addr 0352H /* Timer B1 register */
|
||
|
#pragma ADDRESS tb2_addr 0354H /* Timer B2 register */
|
||
|
#pragma ADDRESS ta0mr_addr 0356H /* Timer A0 mode register */
|
||
|
#pragma ADDRESS ta1mr_addr 0357H /* Timer A1 mode register */
|
||
|
#pragma ADDRESS ta2mr_addr 0358H /* Timer A2 mode register */
|
||
|
#pragma ADDRESS ta3mr_addr 0359H /* Timer A3 mode register */
|
||
|
#pragma ADDRESS ta4mr_addr 035aH /* Timer A4 mode register */
|
||
|
#pragma ADDRESS tb0mr_addr 035bH /* Timer B0 mode register */
|
||
|
#pragma ADDRESS tb1mr_addr 035cH /* Timer B1 mode register */
|
||
|
#pragma ADDRESS tb2mr_addr 035dH /* Timer B2 mode register */
|
||
|
#pragma ADDRESS tb2sc_addr 035eH /* Timer B2 special mode register */
|
||
|
#pragma ADDRESS tcspr_addr 035fH /* Count source prescaler register */
|
||
|
|
||
|
#pragma ADDRESS u0smr4_addr 0364H /* UART0 special mode register 4 */
|
||
|
#pragma ADDRESS u0smr3_addr 0365H /* UART0 special mode register 3 */
|
||
|
#pragma ADDRESS u0smr2_addr 0366H /* UART0 special mode register 2 */
|
||
|
#pragma ADDRESS u0smr_addr 0367H /* UART0 special mode register */
|
||
|
#pragma ADDRESS u0mr_addr 0368H /* UART0 transmit/receive mode register */
|
||
|
#pragma ADDRESS u0brg_addr 0369H /* UART0 bit rate generator */
|
||
|
#pragma ADDRESS u0tb_addr 036aH /* UART0 transmit buffer register */
|
||
|
#pragma ADDRESS u0c0_addr 036cH /* UART0 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u0c1_addr 036dH /* UART0 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u0rb_addr 036eH /* UART0 receive buffer register */
|
||
|
#pragma ADDRESS plc0_addr 0376H /* PLL control register 0 */
|
||
|
#pragma ADDRESS plc1_addr 0377H /* PLL control register 1 */
|
||
|
#pragma ADDRESS dm0sl_addr 0378H /* DMA0 cause select register */
|
||
|
#pragma ADDRESS dm1sl_addr 0379H /* DMA1 cause select register */
|
||
|
#pragma ADDRESS dm2sl_addr 037aH /* DMA1 cause select register */
|
||
|
#pragma ADDRESS dm3sl_addr 037bH /* DMA1 cause select register */
|
||
|
#pragma ADDRESS crcd_addr 037cH /* CRC data register */
|
||
|
#pragma ADDRESS crcin_addr 037eH /* CRC input register */
|
||
|
#pragma ADDRESS ad00_addr 0380H /* A/D0 register 0 */
|
||
|
#pragma ADDRESS ad01_addr 0382H /* A/D0 register 1 */
|
||
|
#pragma ADDRESS ad02_addr 0384H /* A/D0 register 2 */
|
||
|
#pragma ADDRESS ad03_addr 0386H /* A/D0 register 3 */
|
||
|
#pragma ADDRESS ad04_addr 0388H /* A/D0 register 4 */
|
||
|
#pragma ADDRESS ad05_addr 038aH /* A/D0 register 5 */
|
||
|
#pragma ADDRESS ad06_addr 038cH /* A/D0 register 6 */
|
||
|
#pragma ADDRESS ad07_addr 038eH /* A/D0 register 7 */
|
||
|
#pragma ADDRESS ad0con2_addr 0394H /* A/D0 control register 2 */
|
||
|
#pragma ADDRESS ad0con0_addr 0396H /* A/D0 control register 0 */
|
||
|
#pragma ADDRESS ad0con1_addr 0397H /* A/D0 control register 1 */
|
||
|
#pragma ADDRESS da0_addr 0398H /* D/A register 0 */
|
||
|
#pragma ADDRESS da1_addr 039aH /* D/A register 1 */
|
||
|
#pragma ADDRESS dacon_addr 039cH /* D/A control register */
|
||
|
|
||
|
#pragma ADDRESS ps8_addr 03a0H /* Function select register A8 */
|
||
|
#pragma ADDRESS ps9_addr 03a1H /* Function select register A9 */
|
||
|
|
||
|
#pragma ADDRESS psc_addr 03afH /* Function select register C */
|
||
|
#pragma ADDRESS ps0_addr 03b0H /* Function select register A0 */
|
||
|
#pragma ADDRESS ps1_addr 03b1H /* Function select register A1 */
|
||
|
#pragma ADDRESS psl0_addr 03b2H /* Function select register B0 */
|
||
|
#pragma ADDRESS psl1_addr 03b3H /* Function select register B1 */
|
||
|
#pragma ADDRESS ps2_addr 03b4H /* Function select register A2 */
|
||
|
#pragma ADDRESS ps3_addr 03b5H /* Function select register A3 */
|
||
|
#pragma ADDRESS psl2_addr 03b6H /* Function select register B2 */
|
||
|
#pragma ADDRESS psl3_addr 03b7H /* Function select register B3 */
|
||
|
|
||
|
#pragma ADDRESS ps5_addr 03b9H /* Function select register A5 */
|
||
|
|
||
|
#pragma ADDRESS ps6_addr 03bcH /* Function select register A6 */
|
||
|
#pragma ADDRESS ps7_addr 03bdH /* Function select register A7 */
|
||
|
|
||
|
#pragma ADDRESS p6_addr 03c0H /* Port P6 register */
|
||
|
#pragma ADDRESS p7_addr 03c1H /* Port P7 register */
|
||
|
#pragma ADDRESS pd6_addr 03c2H /* Port P6 direction register */
|
||
|
#pragma ADDRESS pd7_addr 03c3H /* Port P7 direction register */
|
||
|
#pragma ADDRESS p8_addr 03c4H /* Port P8 register */
|
||
|
#pragma ADDRESS p9_addr 03c5H /* Port P9 register */
|
||
|
#pragma ADDRESS pd8_addr 03c6H /* Port P8 direction register */
|
||
|
#pragma ADDRESS pd9_addr 03c7H /* Port P9 direction register */
|
||
|
#pragma ADDRESS p10_addr 03c8H /* Port P10 register */
|
||
|
#pragma ADDRESS p11_addr 03c9H /* Port P11 register */
|
||
|
#pragma ADDRESS pd10_addr 03caH /* Port P10 direction register */
|
||
|
#pragma ADDRESS pd11_addr 03cbH /* Port P11 direction register */
|
||
|
#pragma ADDRESS p12_addr 03ccH /* Port P12 register */
|
||
|
#pragma ADDRESS p13_addr 03cdH /* Port P13 register */
|
||
|
#pragma ADDRESS pd12_addr 03ceH /* Port P12 direction register */
|
||
|
#pragma ADDRESS pd13_addr 03cfH /* Port P13 direction register */
|
||
|
#pragma ADDRESS p14_addr 03d0H /* Port P14 register */
|
||
|
#pragma ADDRESS p15_addr 03d1H /* Port P15 register */
|
||
|
#pragma ADDRESS pd14_addr 03d2H /* Port P14 direction register */
|
||
|
#pragma ADDRESS pd15_addr 03d3H /* Port P15 direction register */
|
||
|
#pragma ADDRESS pur2_addr 03daH /* Pull-up control register 2 */
|
||
|
#pragma ADDRESS pur3_addr 03dbH /* Pull-up control register 3 */
|
||
|
#pragma ADDRESS pur4_addr 03dcH /* Pull-up control register 4 */
|
||
|
#pragma ADDRESS p0_addr 03e0H /* Port P0 register */
|
||
|
#pragma ADDRESS p1_addr 03e1H /* Port P1 register */
|
||
|
#pragma ADDRESS pd0_addr 03e2H /* Port P0 direction register */
|
||
|
#pragma ADDRESS pd1_addr 03e3H /* Port P1 direction register */
|
||
|
#pragma ADDRESS p2_addr 03e4H /* Port P2 register */
|
||
|
#pragma ADDRESS p3_addr 03e5H /* Port P3 register */
|
||
|
#pragma ADDRESS pd2_addr 03e6H /* Port P2 direction register */
|
||
|
#pragma ADDRESS pd3_addr 03e7H /* Port P3 direction register */
|
||
|
#pragma ADDRESS p4_addr 03e8H /* Port P4 register */
|
||
|
#pragma ADDRESS p5_addr 03e9H /* Port P5 register */
|
||
|
#pragma ADDRESS pd4_addr 03eaH /* Port P4 direction register */
|
||
|
#pragma ADDRESS pd5_addr 03ebH /* Port P5 direction register */
|
||
|
#pragma ADDRESS pur0_addr 03f0H /* Pull-up control register 0 */
|
||
|
#pragma ADDRESS pur1_addr 03f1H /* Pull-up control register 1 */
|
||
|
#pragma ADDRESS pcr_addr 03ffH /* Port control register */
|
||
|
/*******************************************************
|
||
|
* declare SFR char *
|
||
|
********************************************************/
|
||
|
unsigned char da0_addr; /* D/A register 0 */
|
||
|
#define da0 da0_addr
|
||
|
|
||
|
unsigned char da1_addr; /* D/A register 1 */
|
||
|
#define da1 da1_addr
|
||
|
|
||
|
/********************************************************
|
||
|
* declare SFR short *
|
||
|
********************************************************/
|
||
|
/*---------------------------------------------------------------------
|
||
|
Timer registers ; Read and write to this register in 16-bit units.
|
||
|
-----------------------------------------------------------------------*/
|
||
|
unsigned short ta11_addr; /* Timer A1-1 register */
|
||
|
#define ta11 ta11_addr
|
||
|
|
||
|
unsigned short ta21_addr; /* Timer A2-1 register */
|
||
|
#define ta21 ta21_addr
|
||
|
|
||
|
unsigned short ta41_addr; /* Timer A4-1 register */
|
||
|
#define ta41 ta41_addr
|
||
|
|
||
|
unsigned short tb3_addr; /* Timer B3 register */
|
||
|
#define tb3 tb3_addr
|
||
|
|
||
|
unsigned short tb4_addr; /* Timer B4 register */
|
||
|
#define tb4 tb4_addr
|
||
|
|
||
|
unsigned short tb5_addr; /* Timer B5 register */
|
||
|
#define tb5 tb5_addr
|
||
|
|
||
|
unsigned short ta0_addr; /* Timer A0 register */
|
||
|
#define ta0 ta0_addr
|
||
|
|
||
|
unsigned short ta1_addr; /* Timer A1 register */
|
||
|
#define ta1 ta1_addr
|
||
|
|
||
|
unsigned short ta2_addr; /* Timer A2 register */
|
||
|
#define ta2 ta2_addr
|
||
|
|
||
|
unsigned short ta3_addr; /* Timer A3 register */
|
||
|
#define ta3 ta3_addr
|
||
|
|
||
|
unsigned short ta4_addr; /* Timer A4 register */
|
||
|
#define ta4 ta4_addr
|
||
|
|
||
|
unsigned short tb0_addr; /* Timer B0 register */
|
||
|
#define tb0 tb0_addr
|
||
|
|
||
|
unsigned short tb1_addr; /* Timer B1 register */
|
||
|
#define tb1 tb1_addr
|
||
|
|
||
|
unsigned short tb2_addr; /* Timer B2 register */
|
||
|
#define tb2 tb2_addr
|
||
|
|
||
|
/*---------------------------------------------------------------------
|
||
|
IIO registers ; Read and write to this register in 16-bit units.
|
||
|
-----------------------------------------------------------------------*/
|
||
|
union{
|
||
|
struct{
|
||
|
char low; /* Low 8 bit */
|
||
|
char high; /* High 8 bit */
|
||
|
}byte;
|
||
|
unsigned short word;
|
||
|
}g0bt_addr,g1bt_addr,
|
||
|
g0tm0_addr,g0tm1_addr,g0tm2_addr,g0tm3_addr,g0tm4_addr,g0tm5_addr,g0tm6_addr,g0tm7_addr,
|
||
|
g1tm0_addr,g1tm1_addr,g1tm2_addr,g1tm3_addr,g1tm4_addr,g1tm5_addr,g1tm6_addr,g1tm7_addr,
|
||
|
g0po0_addr,g0po1_addr,g0po2_addr,g0po3_addr,g0po4_addr,g0po5_addr,g0po6_addr,g0po7_addr,
|
||
|
g1po0_addr,g1po1_addr,g1po2_addr,g1po3_addr,g1po4_addr,g1po5_addr,g1po6_addr,g1po7_addr,
|
||
|
g0tcrc_addr,g1tcrc_addr,g0rcrc_addr,g1rcrc_addr,
|
||
|
g2bt_addr,
|
||
|
g2po0_addr,g2po1_addr,g2po2_addr,g2po3_addr,g2po4_addr,g2po5_addr,g2po6_addr,g2po7_addr,
|
||
|
iear_addr,
|
||
|
g3bt_addr,
|
||
|
g3po0_addr,g3po1_addr,g3po2_addr,g3po3_addr,g3po4_addr,g3po5_addr,g3po6_addr,g3po7_addr,
|
||
|
g3mk4_addr,g3mk5_addr,g3mk6_addr,g3mk7_addr,
|
||
|
g3tb_addr,g3rb_addr,hcnt_addr,hadr0_addr,hadr1_addr,hadr2_addr,hadr3_addr,
|
||
|
hmsk0_addr,hmsk1_addr,hmsk2_addr,hmsk3_addr;
|
||
|
|
||
|
/********************************************************
|
||
|
* group 0 and 1 *
|
||
|
********************************************************/
|
||
|
#define g0bt g0bt_addr.word /* Group 0 base timer register */
|
||
|
#define g0btl g0bt_addr.byte.low
|
||
|
#define g0bth g0bt_addr.byte.high
|
||
|
|
||
|
#define g1bt g1bt_addr.word /* Group 1 base timer register */
|
||
|
#define g1btl g1bt_addr.byte.low
|
||
|
#define g1bth g1bt_addr.byte.high
|
||
|
|
||
|
#define g0tm0 g0tm0_addr.word /* Group 0 time measurement register 0 */
|
||
|
#define g0tm0l g0tm0_addr.byte.low
|
||
|
#define g0tm0h g0tm0_addr.byte.high
|
||
|
|
||
|
#define g0tm1 g0tm1_addr.word /* Group 0 time measurement register 1 */
|
||
|
#define g0tm1l g0tm1_addr.byte.low
|
||
|
#define g0tm1h g0tm1_addr.byte.high
|
||
|
|
||
|
#define g0tm2 g0tm2_addr.word /* Group 0 time measurement register 2 */
|
||
|
#define g0tm2l g0tm2_addr.byte.low
|
||
|
#define g0tm2h g0tm2_addr.byte.high
|
||
|
|
||
|
#define g0tm3 g0tm3_addr.word /* Group 0 time measurement register 3 */
|
||
|
#define g0tm3l g0tm3_addr.byte.low
|
||
|
#define g0tm3h g0tm3_addr.byte.high
|
||
|
|
||
|
#define g0tm4 g0tm4_addr.word /* Group 0 time measurement register 4 */
|
||
|
#define g0tm4l g0tm4_addr.byte.low
|
||
|
#define g0tm4h g0tm4_addr.byte.high
|
||
|
|
||
|
#define g0tm5 g0tm5_addr.word /* Group 0 time measurement register 5 */
|
||
|
#define g0tm5l g0tm5_addr.byte.low
|
||
|
#define g0tm5h g0tm5_addr.byte.high
|
||
|
|
||
|
#define g0tm6 g0tm6_addr.word /* Group 0 time measurement register 6 */
|
||
|
#define g0tm6l g0tm6_addr.byte.low
|
||
|
#define g0tm6h g0tm6_addr.byte.high
|
||
|
|
||
|
#define g0tm7 g0tm7_addr.word /* Group 0 time measurement register 7 */
|
||
|
#define g0tm7l g0tm7_addr.byte.low
|
||
|
#define g0tm7h g0tm7_addr.byte.high
|
||
|
|
||
|
#define g1tm0 g1tm0_addr.word /* Group 1 time measurement register 0 */
|
||
|
#define g1tm0l g1tm0_addr.byte.low
|
||
|
#define g1tm0h g1tm0_addr.byte.high
|
||
|
|
||
|
#define g1tm1 g1tm1_addr.word /* Group 1 time measurement register 1 */
|
||
|
#define g1tm1l g1tm1_addr.byte.low
|
||
|
#define g1tm1h g1tm1_addr.byte.high
|
||
|
|
||
|
#define g1tm2 g1tm2_addr.word /* Group 1 time measurement register 2 */
|
||
|
#define g1tm2l g1tm2_addr.byte.low
|
||
|
#define g1tm2h g1tm2_addr.byte.high
|
||
|
|
||
|
#define g1tm3 g1tm3_addr.word /* Group 1 time measurement register 3 */
|
||
|
#define g1tm3l g1tm3_addr.byte.low
|
||
|
#define g1tm3h g1tm3_addr.byte.high
|
||
|
|
||
|
#define g1tm4 g1tm4_addr.word /* Group 1 time measurement register 4 */
|
||
|
#define g1tm4l g1tm4_addr.byte.low
|
||
|
#define g1tm4h g1tm4_addr.byte.high
|
||
|
|
||
|
#define g1tm5 g1tm5_addr.word /* Group 1 time measurement register 5 */
|
||
|
#define g1tm5l g1tm5_addr.byte.low
|
||
|
#define g1tm5h g1tm5_addr.byte.high
|
||
|
|
||
|
#define g1tm6 g1tm6_addr.word /* Group 1 time measurement register 6 */
|
||
|
#define g1tm6l g1tm6_addr.byte.low
|
||
|
#define g1tm6h g1tm6_addr.byte.high
|
||
|
|
||
|
#define g1tm7 g1tm7_addr.word /* Group 1 time measurement register 7 */
|
||
|
#define g1tm7l g1tm7_addr.byte.low
|
||
|
#define g1tm7h g1tm7_addr.byte.high
|
||
|
|
||
|
#define g0po0 g0po0_addr.word /* Group 0 waveform generate register 0 */
|
||
|
#define g0po0l g0po0_addr.byte.low
|
||
|
#define g0po0h g0po0_addr.byte.high
|
||
|
|
||
|
#define g0po1 g0po1_addr.word /* Group 0 waveform generate register 1 */
|
||
|
#define g0po1l g0po1_addr.byte.low
|
||
|
#define g0po1h g0po1_addr.byte.high
|
||
|
|
||
|
#define g0po2 g0po2_addr.word /* Group 0 waveform generate register 2 */
|
||
|
#define g0po2l g0po2_addr.byte.low
|
||
|
#define g0po2h g0po2_addr.byte.high
|
||
|
|
||
|
#define g0po3 g0po3_addr.word /* Group 0 waveform generate register 3 */
|
||
|
#define g0po3l g0po3_addr.byte.low
|
||
|
#define g0po3h g0po3_addr.byte.high
|
||
|
|
||
|
#define g0po4 g0po4_addr.word /* Group 0 waveform generate register 4 */
|
||
|
#define g0po4l g0po4_addr.byte.low
|
||
|
#define g0po4h g0po4_addr.byte.high
|
||
|
|
||
|
#define g0po5 g0po5_addr.word /* Group 0 waveform generate register 5 */
|
||
|
#define g0po5l g0po5_addr.byte.low
|
||
|
#define g0po5h g0po5_addr.byte.high
|
||
|
|
||
|
#define g0po6 g0po6_addr.word /* Group 0 waveform generate register 6 */
|
||
|
#define g0po6l g0po6_addr.byte.low
|
||
|
#define g0po6h g0po6_addr.byte.high
|
||
|
|
||
|
#define g0po7 g0po7_addr.word /* Group 0 waveform generate register 7 */
|
||
|
#define g0po7l g0po7_addr.byte.low
|
||
|
#define g0po7h g0po7_addr.byte.high
|
||
|
|
||
|
#define g1po0 g1po0_addr.word /* Group 1 waveform generate register 0 */
|
||
|
#define g1po0l g1po0_addr.byte.low
|
||
|
#define g1po0h g1po0_addr.byte.high
|
||
|
|
||
|
#define g1po1 g1po1_addr.word /* Group 1 waveform generate register 1 */
|
||
|
#define g1po1l g1po1_addr.byte.low
|
||
|
#define g1po1h g1po1_addr.byte.high
|
||
|
|
||
|
#define g1po2 g1po2_addr.word /* Group 1 waveform generate register 2 */
|
||
|
#define g1po2l g1po2_addr.byte.low
|
||
|
#define g1po2h g1po2_addr.byte.high
|
||
|
|
||
|
#define g1po3 g1po3_addr.word /* Group 1 waveform generate register 3 */
|
||
|
#define g1po3l g1po3_addr.byte.low
|
||
|
#define g1po3h g1po3_addr.byte.high
|
||
|
|
||
|
#define g1po4 g1po4_addr.word /* Group 1 waveform generate register 4 */
|
||
|
#define g1po4l g1po4_addr.byte.low
|
||
|
#define g1po4h g1po4_addr.byte.high
|
||
|
|
||
|
#define g1po5 g1po5_addr.word /* Group 1 waveform generate register 5 */
|
||
|
#define g1po5l g1po5_addr.byte.low
|
||
|
#define g1po5h g1po5_addr.byte.high
|
||
|
|
||
|
#define g1po6 g1po6_addr.word /* Group 1 waveform generate register 6 */
|
||
|
#define g1po6l g1po6_addr.byte.low
|
||
|
#define g1po6h g1po6_addr.byte.high
|
||
|
|
||
|
#define g1po7 g1po7_addr.word /* Group 1 waveform generate register 7 */
|
||
|
#define g1po7l g1po7_addr.byte.low
|
||
|
#define g1po7h g1po7_addr.byte.high
|
||
|
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
SI/O receive buffer register
|
||
|
------------------------------------------------------*/
|
||
|
union{
|
||
|
struct{
|
||
|
char b0:1;
|
||
|
char b1:1;
|
||
|
char b2:1;
|
||
|
char b3:1;
|
||
|
char b4:1;
|
||
|
char b5:1;
|
||
|
char b6:1;
|
||
|
char b7:1;
|
||
|
char b8:1;
|
||
|
char b9:1;
|
||
|
char b10:1;
|
||
|
char b11:1;
|
||
|
char oer:1; /* Overrun error flag */
|
||
|
char fer:1; /* Framing error flag */
|
||
|
char per:1; /* Parity error flag */
|
||
|
char sum:1; /* Error sum flag */
|
||
|
}bit;
|
||
|
struct{
|
||
|
char low; /* Low 8 bit */
|
||
|
char high; /* High 8 bit */
|
||
|
}byte;
|
||
|
unsigned short word;
|
||
|
}g0rb_addr,g1rb_addr;
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
g0rb
|
||
|
------------------------------------------------------*/
|
||
|
#define g0rb g0rb_addr.word
|
||
|
#define g0rbl g0rb_addr.byte.low
|
||
|
#define g0rbh g0rb_addr.byte.high
|
||
|
|
||
|
#define oer_g0rb g0rb_addr.bit.oer /* Overrun error flag */
|
||
|
#define fer_g0rb g0rb_addr.bit.fer /* Framing error flag */
|
||
|
//#define per_g0rb g0rb_addr.bit.per /* Parity error flag */
|
||
|
//#define sum_g0rb g0rb_addr.bit.sum /* Error sum flag */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
g1rb
|
||
|
------------------------------------------------------*/
|
||
|
#define g1rb g1rb_addr.word
|
||
|
#define g1rbl g1rb_addr.byte.low
|
||
|
#define g1rbh g1rb_addr.byte.high
|
||
|
|
||
|
#define oer_g1rb g1rb_addr.bit.oer /* Overrun error flag */
|
||
|
#define fer_g1rb g1rb_addr.bit.fer /* Framing error flag */
|
||
|
//#define per_g1rb g1rb_addr.bit.per /* Parity error flag */
|
||
|
//#define sum_g1rb g1rb_addr.bit.sum /* Error sum flag */
|
||
|
|
||
|
|
||
|
#define g0tcrc g0tcrc_addr.word /* Group 0 transmit CRC code register */
|
||
|
#define g0tcrcl g0tcrc_addr.byte.low
|
||
|
#define g0tcrch g0tcrc_addr.byte.high
|
||
|
|
||
|
#define g1tcrc g1tcrc_addr.word /* Group 1 transmit CRC code register */
|
||
|
#define g1tcrcl g1tcrc_addr.byte.low
|
||
|
#define g1tcrch g1tcrc_addr.byte.high
|
||
|
|
||
|
|
||
|
#define g0rcrc g0rcrc_addr.word /* Group 0 receive CRC code register */
|
||
|
#define g0rcrcl g0rcrc_addr.byte.low
|
||
|
#define g0rcrch g0rcrc_addr.byte.high
|
||
|
|
||
|
#define g1rcrc g1rcrc_addr.word /* Group 1 receive CRC code register */
|
||
|
#define g1rcrcl g1rcrc_addr.byte.low
|
||
|
#define g1rcrch g1rcrc_addr.byte.high
|
||
|
|
||
|
/********************************************************
|
||
|
* group 2 *
|
||
|
********************************************************/
|
||
|
|
||
|
#define g2bt g2bt_addr.word /* Group 2 base timer register */
|
||
|
#define g2btl g2bt_addr.byte.low
|
||
|
#define g2bth g2bt_addr.byte.high
|
||
|
|
||
|
#define g2po0 g2po0_addr.word /* Group 2 waveform generate register 0 */
|
||
|
#define g2po0l g2po0_addr.byte.low
|
||
|
#define g2po0h g2po0_addr.byte.high
|
||
|
|
||
|
#define g2po1 g2po1_addr.word /* Group 2 waveform generate register 1 */
|
||
|
#define g2po1l g2po1_addr.byte.low
|
||
|
#define g2po1h g2po1_addr.byte.high
|
||
|
|
||
|
#define g2po2 g2po2_addr.word /* Group 2 waveform generate register 2 */
|
||
|
#define g2po2l g2po2_addr.byte.low
|
||
|
#define g2po2h g2po2_addr.byte.high
|
||
|
|
||
|
#define g2po3 g2po3_addr.word /* Group 2 waveform generate register 3 */
|
||
|
#define g2po3l g2po3_addr.byte.low
|
||
|
#define g2po3h g2po3_addr.byte.high
|
||
|
|
||
|
#define g2po4 g2po4_addr.word /* Group 2 waveform generate register 4 */
|
||
|
#define g2po4l g2po4_addr.byte.low
|
||
|
#define g2po4h g2po4_addr.byte.high
|
||
|
|
||
|
#define g2po5 g2po5_addr.word /* Group 2 waveform generate register 5 */
|
||
|
#define g2po5l g2po5_addr.byte.low
|
||
|
#define g2po5h g2po5_addr.byte.high
|
||
|
|
||
|
#define g2po6 g2po6_addr.word /* Group 2 waveform generate register 6 */
|
||
|
#define g2po6l g2po6_addr.byte.low
|
||
|
#define g2po6h g2po6_addr.byte.high
|
||
|
|
||
|
#define g2po7 g2po7_addr.word /* Group 2 waveform generate register 7 */
|
||
|
#define g2po7l g2po7_addr.byte.low
|
||
|
#define g2po7h g2po7_addr.byte.high
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Group 2 SI/O transmit buffer register
|
||
|
------------------------------------------------------*/
|
||
|
union{
|
||
|
struct{
|
||
|
char b0:1;
|
||
|
char b1:1;
|
||
|
char b2:1;
|
||
|
char b3:1;
|
||
|
char b4:1;
|
||
|
char b5:1;
|
||
|
char b6:1;
|
||
|
char b7:1;
|
||
|
char sz0:1;
|
||
|
char sz1:1;
|
||
|
char sz2:1;
|
||
|
char b11:1;
|
||
|
char b12:1;
|
||
|
char a:1;
|
||
|
char pc:1;
|
||
|
char p:1;
|
||
|
}bit;
|
||
|
struct{
|
||
|
char low; /* Low 8 bit */
|
||
|
char high; /* High 8 bit */
|
||
|
}byte;
|
||
|
unsigned short word;
|
||
|
}g2tb_addr;
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
g2tb
|
||
|
------------------------------------------------------*/
|
||
|
#define g2tb g2tb_addr.word
|
||
|
#define g2tbl g2tb_addr.byte.low
|
||
|
#define g2tbh g2tb_addr.byte.high
|
||
|
|
||
|
#define sz0_g2tb g2tb_addr.bit.sz0
|
||
|
#define sz1_g2tb g2tb_addr.bit.sz1
|
||
|
#define sz2_g2tb g2tb_addr.bit.sz2
|
||
|
#define a_g2tb g2tb_addr.bit.a
|
||
|
#define pc_g2tb g2tb_addr.bit.pc
|
||
|
#define p_g2tb g2tb_addr.bit.p
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Group 2 SI/O receive buffer register
|
||
|
------------------------------------------------------*/
|
||
|
union{
|
||
|
struct{
|
||
|
char b0:1;
|
||
|
char b1:1;
|
||
|
char b2:1;
|
||
|
char b3:1;
|
||
|
char b4:1;
|
||
|
char b5:1;
|
||
|
char b6:1;
|
||
|
char b7:1;
|
||
|
char b8:1;
|
||
|
char b9:1;
|
||
|
char b10:1;
|
||
|
char b11:1;
|
||
|
char oer:1;
|
||
|
char b13:1;
|
||
|
char b14:1;
|
||
|
char b15:1;
|
||
|
}bit;
|
||
|
struct{
|
||
|
char low; /* Low 8 bit */
|
||
|
char high; /* High 8 bit */
|
||
|
}byte;
|
||
|
unsigned short word;
|
||
|
}g2rb_addr;
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
g2rb
|
||
|
------------------------------------------------------*/
|
||
|
#define g2rb g2rb_addr.word
|
||
|
#define g2rbl g2rb_addr.byte.low
|
||
|
#define g2rbh g2rb_addr.byte.high
|
||
|
|
||
|
#define oer_g2rb g2rb_addr.bit.oer
|
||
|
|
||
|
#define iear iear_addr.word /* Group 2 IEBus address register */
|
||
|
#define iearl iear_addr.byte.low
|
||
|
#define iearh iear_addr.byte.high
|
||
|
|
||
|
|
||
|
/********************************************************
|
||
|
* group 3 *
|
||
|
********************************************************/
|
||
|
|
||
|
#define g3bt g3bt_addr.word /* Group 3 base timer register */
|
||
|
#define g3btl g3bt_addr.byte.low
|
||
|
#define g3bth g3bt_addr.byte.high
|
||
|
|
||
|
#define g3po0 g3po0_addr.word /* Group 3 waveform generate register 0 */
|
||
|
#define g3po0l g3po0_addr.byte.low
|
||
|
#define g3po0h g3po0_addr.byte.high
|
||
|
|
||
|
#define g3po1 g3po1_addr.word /* Group 3 waveform generate register 1 */
|
||
|
#define g3po1l g3po1_addr.byte.low
|
||
|
#define g3po1h g3po1_addr.byte.high
|
||
|
|
||
|
#define g3po2 g3po2_addr.word /* Group 3 waveform generate register 2 */
|
||
|
#define g3po2l g3po2_addr.byte.low
|
||
|
#define g3po2h g3po2_addr.byte.high
|
||
|
|
||
|
#define g3po3 g3po3_addr.word /* Group 3 waveform generate register 3 */
|
||
|
#define g3po3l g3po3_addr.byte.low
|
||
|
#define g3po3h g3po3_addr.byte.high
|
||
|
|
||
|
#define g3po4 g3po4_addr.word /* Group 3 waveform generate register 4 */
|
||
|
#define g3po4l g3po4_addr.byte.low
|
||
|
#define g3po4h g3po4_addr.byte.high
|
||
|
|
||
|
#define g3po5 g3po5_addr.word /* Group 3 waveform generate register 5 */
|
||
|
#define g3po5l g3po5_addr.byte.low
|
||
|
#define g3po5h g3po5_addr.byte.high
|
||
|
|
||
|
#define g3po6 g3po6_addr.word /* Group 3 waveform generate register 6 */
|
||
|
#define g3po6l g3po6_addr.byte.low
|
||
|
#define g3po6h g3po6_addr.byte.high
|
||
|
|
||
|
#define g3po7 g3po7_addr.word /* Group 3 waveform generate register 7 */
|
||
|
#define g3po7l g3po7_addr.byte.low
|
||
|
#define g3po7h g3po7_addr.byte.high
|
||
|
|
||
|
|
||
|
#define g3mk4 g3mk4_addr.word /* Group 3 waveform generate mask register 4 */
|
||
|
#define g3mk4l g3mk4_addr.byte.low
|
||
|
#define g3mk4h g3mk4_addr.byte.high
|
||
|
|
||
|
#define g3mk5 g3mk5_addr.word /* Group 3 waveform generate mask register 5 */
|
||
|
#define g3mk5l g3mk5_addr.byte.low
|
||
|
#define g3mk5h g3mk5_addr.byte.high
|
||
|
|
||
|
#define g3mk6 g3mk6_addr.word /* Group 3 waveform generate mask register 6 */
|
||
|
#define g3mk6l g3mk6_addr.byte.low
|
||
|
#define g3mk6h g3mk6_addr.byte.high
|
||
|
|
||
|
#define g3mk7 g3mk7_addr.word /* Group 3 waveform generate mask register 7 */
|
||
|
#define g3mk7l g3mk7_addr.byte.low
|
||
|
#define g3mk7h g3mk7_addr.byte.high
|
||
|
|
||
|
|
||
|
#define g3tb g3tb_addr.word /* Group 3 SI/O transmit buffer register */
|
||
|
#define g3tbl g3tb_addr.byte.low
|
||
|
#define g3tbh g3tb_addr.byte.high
|
||
|
|
||
|
#define g3rb g3rb_addr.word /* Group 3 SI/O receive buffer register */
|
||
|
#define g3rbl g3rb_addr.byte.low
|
||
|
#define g3rbh g3rb_addr.byte.high
|
||
|
|
||
|
#define hcnt hcnt_addr.word /* Group 3 high-speed HDLC transmit counter */
|
||
|
#define hcntl hcnt_addr.byte.low
|
||
|
#define hcnth hcnt_addr.byte.high
|
||
|
|
||
|
#define hadr0 hadr0_addr.word /* Group 3 high-speed HDLC data compare register 0 */
|
||
|
#define hadr0l hadr0_addr.byte.low
|
||
|
#define hadr0h hadr0_addr.byte.high
|
||
|
|
||
|
#define hadr1 hadr1_addr.word /* Group 3 high-speed HDLC data compare register 1 */
|
||
|
#define hadr1l hadr1_addr.byte.low
|
||
|
#define hadr1h hadr1_addr.byte.high
|
||
|
|
||
|
#define hadr2 hadr2_addr.word /* Group 3 high-speed HDLC data compare register 2 */
|
||
|
#define hadr2l hadr2_addr.byte.low
|
||
|
#define hadr2h hadr2_addr.byte.high
|
||
|
|
||
|
#define hadr3 hadr3_addr.word /* Group 3 high-speed HDLC data compare register 3 */
|
||
|
#define hadr3l hadr3_addr.byte.low
|
||
|
#define hadr3h hadr3_addr.byte.high
|
||
|
|
||
|
#define hmsk0 hmsk0_addr.word /* Group 3 high-speed HDLC data mask register 0 */
|
||
|
#define hmsk0l hmsk0_addr.byte.low
|
||
|
#define hmsk0h hmsk0_addr.byte.high
|
||
|
|
||
|
#define hmsk1 hmsk1_addr.word /* Group 3 high-speed HDLC data mask register 1 */
|
||
|
#define hmsk1l hmsk1_addr.byte.low
|
||
|
#define hmsk1h hmsk1_addr.byte.high
|
||
|
|
||
|
#define hmsk2 hmsk2_addr.word /* Group 3 high-speed HDLC data mask register 2 */
|
||
|
#define hmsk2l hmsk2_addr.byte.low
|
||
|
#define hmsk2h hmsk2_addr.byte.high
|
||
|
|
||
|
#define hmsk3 hmsk3_addr.word /* Group 3 high-speed HDLC data mask register 3 */
|
||
|
#define hmsk3l hmsk3_addr.byte.low
|
||
|
#define hmsk3h hmsk3_addr.byte.high
|
||
|
|
||
|
|
||
|
/********************************************************
|
||
|
* declare SFR bit *
|
||
|
********************************************************/
|
||
|
struct bit_def {
|
||
|
char b0:1;
|
||
|
char b1:1;
|
||
|
char b2:1;
|
||
|
char b3:1;
|
||
|
char b4:1;
|
||
|
char b5:1;
|
||
|
char b6:1;
|
||
|
char b7:1;
|
||
|
};
|
||
|
union byte_def{
|
||
|
struct bit_def bit;
|
||
|
char byte;
|
||
|
};
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
DRAM control register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def dramcont_addr;
|
||
|
#define dramcont dramcont_addr.byte
|
||
|
|
||
|
#define wt_dramcont dramcont_addr.bit.b0
|
||
|
#define ar0_dramcont dramcont_addr.bit.b1
|
||
|
#define ar1_dramcont dramcont_addr.bit.b2
|
||
|
#define ar2_dramcont dramcont_addr.bit.b3
|
||
|
#define sref_dramcont dramcont_addr.bit.b7
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
DRAM refresh interval set register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def refcnt_addr;
|
||
|
#define refcnt refcnt_addr.byte
|
||
|
|
||
|
//#define refcnt0 refcnt_addr.bit.b0
|
||
|
//#define refcnt1 refcnt_addr.bit.b1
|
||
|
//#define refcnt2 refcnt_addr.bit.b2
|
||
|
//#define refcnt3 refcnt_addr.bit.b3
|
||
|
//#define refcnt4 refcnt_addr.bit.b4
|
||
|
//#define refcnt5 refcnt_addr.bit.b5
|
||
|
//#define refcnt6 refcnt_addr.bit.b6
|
||
|
//#define refcnt7 refcnt_addr.bit.b7
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Flash Memory Control Register 2
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def fmr2_addr;
|
||
|
#define fmr2 fmr2_addr.byte
|
||
|
|
||
|
#define fmr20 fmr2_addr.bit.b0
|
||
|
#define fmr22 fmr2_addr.bit.b2
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Flash Memory Control Register 1
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def fmr1_addr;
|
||
|
#define fmr1 fmr1_addr.byte
|
||
|
|
||
|
#define fmr10 fmr1_addr.bit.b0
|
||
|
#define fmr11 fmr1_addr.bit.b1
|
||
|
#define fmr14 fmr1_addr.bit.b4
|
||
|
#define fmr15 fmr1_addr.bit.b5
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Flash Memory Control Register 0
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def fmr0_addr;
|
||
|
#define fmr0 fmr0_addr.byte
|
||
|
|
||
|
#define fmr00 fmr0_addr.bit.b0
|
||
|
#define fmr01 fmr0_addr.bit.b1
|
||
|
#define fmr02 fmr0_addr.bit.b2
|
||
|
#define fmr03 fmr0_addr.bit.b3
|
||
|
//#define fmr04 fmr0_addr.bit.b4
|
||
|
//#define fmr05 fmr0_addr.bit.b5
|
||
|
#define fmr06 fmr0_addr.bit.b6
|
||
|
//#define fmr07 fmr0_addr.bit.b7
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Processor mode register 0
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def pm0_addr;
|
||
|
#define pm0 pm0_addr.byte
|
||
|
|
||
|
#define pm00 pm0_addr.bit.b0 /* Processor mode bit */
|
||
|
#define pm01 pm0_addr.bit.b1 /* Processor mode bit */
|
||
|
#define pm02 pm0_addr.bit.b2 /* R/W mode select bit */
|
||
|
#define pm03 pm0_addr.bit.b3 /* Software reset bit */
|
||
|
#define pm04 pm0_addr.bit.b4 /* Multiplexed bus space select bit */
|
||
|
#define pm05 pm0_addr.bit.b5 /* Multiplexed bus space select bit */
|
||
|
//#define pm06 pm0_addr.bit.b6 /* Reserved bit */
|
||
|
#define pm07 pm0_addr.bit.b7 /* BCLK output function select bit */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Processor mode register 1
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def pm1_addr;
|
||
|
#define pm1 pm1_addr.byte
|
||
|
|
||
|
#define pm10 pm1_addr.bit.b0 /* External memory area mode bit */
|
||
|
#define pm11 pm1_addr.bit.b1 /* External memory area mode bit */
|
||
|
#define pm12 pm1_addr.bit.b2 /* Internal memory wait bit */
|
||
|
#define pm13 pm1_addr.bit.b3 /* SFR wait bit */
|
||
|
#define pm14 pm1_addr.bit.b4 /* ALE pin select bit */
|
||
|
#define pm15 pm1_addr.bit.b5 /* ALE pin select bit */
|
||
|
#define pm17 pm1_addr.bit.b7 /* Reserved bit */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
System clock control register 0
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def cm0_addr;
|
||
|
#define cm0 cm0_addr.byte
|
||
|
|
||
|
#define cm00 cm0_addr.bit.b0 /* Clock output function select bit */
|
||
|
#define cm01 cm0_addr.bit.b1 /* Clock output function select bit */
|
||
|
#define cm02 cm0_addr.bit.b2 /* WAIT peripheral function clock stop bit */
|
||
|
#define cm04 cm0_addr.bit.b4 /* Port Xc select bit */
|
||
|
#define cm05 cm0_addr.bit.b5 /* Main clock stop bit */
|
||
|
#define cm06 cm0_addr.bit.b6 /* WDT function select bit */
|
||
|
#define cm07 cm0_addr.bit.b7 /* System clock select bit (Xin-Xout or Xcin-Xcout)*/
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
System clock control register 1
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def cm1_addr;
|
||
|
#define cm1 cm1_addr.byte
|
||
|
|
||
|
#define cm10 cm1_addr.bit.b0 /* All clock stop control bit */
|
||
|
//#define cm15 cm1_addr.bit.b5 /* Xin-Xout drive capacity select bit */
|
||
|
#define cm17 cm1_addr.bit.b7 /* System clock select bit (Xin-Xout or PLL clock) */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Oscillation stop detect register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def cm2_addr;
|
||
|
#define cm2 cm2_addr.byte
|
||
|
|
||
|
#define cm20 cm2_addr.bit.b0
|
||
|
#define cm21 cm2_addr.bit.b1
|
||
|
#define cm22 cm2_addr.bit.b2
|
||
|
#define cm23 cm2_addr.bit.b3
|
||
|
#define cm24 cm2_addr.bit.b4
|
||
|
#define cm25 cm2_addr.bit.b5
|
||
|
#define cm26 cm2_addr.bit.b6
|
||
|
#define cm27 cm2_addr.bit.b7
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Wait control register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def wcr_addr;
|
||
|
#define wcr wcr_addr.byte
|
||
|
|
||
|
#define wcr0 wcr_addr.bit.b0
|
||
|
#define wcr1 wcr_addr.bit.b1
|
||
|
#define wcr2 wcr_addr.bit.b2
|
||
|
#define wcr3 wcr_addr.bit.b3
|
||
|
#define wcr4 wcr_addr.bit.b4
|
||
|
#define wcr5 wcr_addr.bit.b5
|
||
|
#define wcr6 wcr_addr.bit.b6
|
||
|
#define wcr7 wcr_addr.bit.b7
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Address match interrupt enable register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def aier_addr;
|
||
|
#define aier aier_addr.byte
|
||
|
|
||
|
#define aier0 aier_addr.bit.b0 /* Address match interrupt 0 enable bit */
|
||
|
#define aier1 aier_addr.bit.b1 /* Address match interrupt 1 enable bit */
|
||
|
#define aier2 aier_addr.bit.b2 /* Address match interrupt 2 enable bit */ /*99.08.30*/
|
||
|
#define aier3 aier_addr.bit.b3 /* Address match interrupt 3 enable bit */ /*99.08.30*/
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
X-Y control register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def xyc_addr;
|
||
|
#define xyc xyc_addr.byte
|
||
|
|
||
|
#define xyc0 xyc_addr.bit.b0
|
||
|
#define xyc1 xyc_addr.bit.b1
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Protect register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def prcr_addr;
|
||
|
#define prcr prcr_addr.byte
|
||
|
|
||
|
#define prc0 prcr_addr.bit.b0 /* Enables writing to system clock control register 0 and 1 */
|
||
|
#define prc1 prcr_addr.bit.b1 /* Enables writing to processor mode register 0 and 1 */
|
||
|
#define prc2 prcr_addr.bit.b2 /* Enables writing to port P9 direction register and function select register A3 */
|
||
|
#define prc3 prcr_addr.bit.b3 /* Enables writing VDC control register and PLL VDC control register */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
External data bus width control register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def ds_addr;
|
||
|
#define ds ds_addr.byte
|
||
|
|
||
|
#define ds0 ds_addr.bit.b0
|
||
|
#define ds1 ds_addr.bit.b1
|
||
|
#define ds2 ds_addr.bit.b2
|
||
|
#define ds3 ds_addr.bit.b3
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Main clock division register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def mcd_addr;
|
||
|
#define mcd mcd_addr.byte
|
||
|
|
||
|
#define mcd0 mcd_addr.bit.b0
|
||
|
#define mcd1 mcd_addr.bit.b1
|
||
|
#define mcd2 mcd_addr.bit.b2
|
||
|
#define mcd3 mcd_addr.bit.b3
|
||
|
#define mcd4 mcd_addr.bit.b4
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
PLL control register 0
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def plc0_addr;
|
||
|
#define plc0 plc0_addr.byte
|
||
|
|
||
|
#define plc00 plc0_addr.bit.b0
|
||
|
#define plc01 plc0_addr.bit.b1
|
||
|
#define plc02 plc0_addr.bit.b2
|
||
|
//#define plc03 plc0_addr.bit.b3
|
||
|
#define plc04 plc0_addr.bit.b4
|
||
|
#define plc05 plc0_addr.bit.b5
|
||
|
#define plc07 plc0_addr.bit.b7
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
PLL control register 1
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def plc1_addr;
|
||
|
#define plc1 plc1_addr.byte
|
||
|
|
||
|
//#define plc10 plc1_addr.bit.b0
|
||
|
#define plc11 plc1_addr.bit.b1
|
||
|
//#define plc12 plc1_addr.bit.b2
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Count source prescaler register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def tcspr_addr;
|
||
|
#define tcspr tcspr_addr.byte
|
||
|
|
||
|
#define cnt0 tcspr_addr.bit.b0
|
||
|
#define cnt1 tcspr_addr.bit.b1
|
||
|
#define cnt2 tcspr_addr.bit.b2
|
||
|
#define cnt3 tcspr_addr.bit.b3
|
||
|
#define cst tcspr_addr.bit.b7
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Exit priority register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def rlvl_addr;
|
||
|
#define rlvl rlvl_addr.byte
|
||
|
|
||
|
#define rlvl0 rlvl_addr.bit.b0
|
||
|
#define rlvl1 rlvl_addr.bit.b1
|
||
|
#define rlvl2 rlvl_addr.bit.b2
|
||
|
#define fsit rlvl_addr.bit.b3
|
||
|
#define dmaii rlvl_addr.bit.b5
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Interrupt cause select register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def ifsr_addr;
|
||
|
#define ifsr ifsr_addr.byte
|
||
|
|
||
|
#define ifsr0 ifsr_addr.bit.b0
|
||
|
#define ifsr1 ifsr_addr.bit.b1
|
||
|
#define ifsr2 ifsr_addr.bit.b2
|
||
|
#define ifsr3 ifsr_addr.bit.b3
|
||
|
#define ifsr4 ifsr_addr.bit.b4
|
||
|
#define ifsr5 ifsr_addr.bit.b5
|
||
|
#define ifsr6 ifsr_addr.bit.b6
|
||
|
#define ifsr7 ifsr_addr.bit.b7
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Timer B2 special mode register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def tb2sc_addr;
|
||
|
#define tb2sc tb2sc_addr.byte
|
||
|
|
||
|
#define pwcon tb2sc_addr.bit.b0
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Watchdog timer start register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def wdts_addr;
|
||
|
#define wdts wdts_addr.byte
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
CRC input register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def crcin_addr;
|
||
|
#define crcin crcin_addr.byte
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Watchdog timer control register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def wdc_addr;
|
||
|
#define wdc wdc_addr.byte
|
||
|
|
||
|
//#define wdc5 wdc_addr.bit.b5
|
||
|
//#define wdc6 wdc_addr.bit.b6
|
||
|
#define wdc7 wdc_addr.bit.b7 /* Prescaler select bit */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
PLL VDC control register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def plv_addr;
|
||
|
#define plv plv_addr.byte
|
||
|
|
||
|
#define plv00 plv_addr.bit.b0
|
||
|
//#define plv01 plv_addr.bit.b1
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Count start flag
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def tabsr_addr;
|
||
|
#define tabsr tabsr_addr.byte
|
||
|
|
||
|
#define ta0s tabsr_addr.bit.b0 /* Timer A0 count start flag */
|
||
|
#define ta1s tabsr_addr.bit.b1 /* Timer A1 count start flag */
|
||
|
#define ta2s tabsr_addr.bit.b2 /* Timer A2 count start flag */
|
||
|
#define ta3s tabsr_addr.bit.b3 /* Timer A3 count start flag */
|
||
|
#define ta4s tabsr_addr.bit.b4 /* Timer A4 count start flag */
|
||
|
#define tb0s tabsr_addr.bit.b5 /* Timer B0 count start flag */
|
||
Formats disponibles : Unified diff
erreur