Révision 136
Ajouté par rademagalh il y a presque 4 ans
| branch/DEMAGALHAES/sp4a12/main.c | ||
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#include <stdio.h>
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#include <stdlib.h>
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#include <strings.h>
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#include "trame.h"
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//Trames de tests ? modifier si n?cessaire.
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char * trames[]= {"$GPGSV,3,2,10,15,03,077,,18,04,041,42,19,85,271,,20,08,214,*7C",
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"$GPGSV,3,3,10,22,39,053,50,28,15,320,*7E",
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"$GPRMC,141914.00,A,4545.6424,N,00306.6036,E,0.4,99.4,010206,,*0C",
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"$GPGLL,4545.6424,N,00306.6036,E,141914.00,A*0E",
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"$GPGGA,141914.00,4545.0000,N,00306.6036,E,1,05,3.4,499.3,M,,M,,*7D",
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"$GPGSA,A,3,,03,,22,14,,01,,18,,,,3.9,3.4,1.9*39",
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"$GPVTG,99.4,T,,M,0.4,N,0.7,K*57",
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"$GPZDA,141914.00,01,02,2006,00,00*69",
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0};
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int trame_cmp(char* a,char* b){
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return 0;
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}
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//Fonction ? modifier !!!!!
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void traitement(char * trame)
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{
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printf ("> %s\n",trame);
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}
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//Ajouter vos tests unitaires dans cette fonction.
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void tests_unitaires(void){
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if (5!=5){
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printf ("Erreur Test unitaire basique.\n");
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exit(-1);
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}
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if (trame_cmp("$GPGGA suite chaine","GPGGA")!=1){
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printf ("Erreur Test unitaire trame_cmp.\n");
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exit(-1);
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}
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if (trame_cmp("$GPRMC suite chaine","GPGGA")!=0){
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printf ("Erreur Test unitaire trame_cmp.\n");
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exit(-1);
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}
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if (trame_cmp("$GPRMC... ", "GPRMC" )!=1){
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printf ("Erreur Test unitaire trame_cmp.\n");
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exit(-1);
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}
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if (trame_cmp("$APRMC...", "GPGGA")!=0){
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printf ("Erreur Test unitaire trame_cmp.\n");
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exit(-1);
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}
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}
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// Ne pas modifier cette fonction
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int main(int argc,char ** argv)
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{
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tests_unitaires();
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// Affichage des trames definies dans la table trames.
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printf ("Trames de tests tableau trames:\n");
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int i=0;
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while (trames[i])
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traitement(trames[i++]);
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if (!trame_init())
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exit(-1);
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// Affichage des trames du fichier gps.log
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char *trame;
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printf ("Trames de tests du fichier gps.log\n");
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while ((trame = trame_suivante()))
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traitement(trame);
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return 0;
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}
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| branch/DEMAGALHAES/sp4a12/gps.log | ||
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$GPGSV,3,2,10,15,03,077,,18,04,041,42,19,85,271,,20,08,214,*7C
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$GPGSV,3,3,10,22,39,053,50,28,15,320,*7E
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$GPRMC,141914.00,A,4545.6424,N,00306.6036,E,0.4,99.4,010206,,*0C
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$GPGLL,4545.6424,N,00306.6036,E,141914.00,A*0E
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$GPGGA,141914.00,4545.0000,N,00306.6036,E,1,05,3.4,499.3,M,,M,,*79
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$GPGSA,A,3,,03,,22,14,,01,,18,,,,3.9,3.4,1.9*39
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$GPVTG,99.4,T,,M,0.4,N,0.7,K*57
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$GPZDA,141914.00,01,02,2006,00,00*69
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$GPGSV,3,1,10,01,13,142,46,03,48,144,47,11,41,277,,14,27,104,42*75
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$GPGSV,3,2,10,15,03,077,,18,04,041,41,19,85,271,,20,08,214,*7F
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$GPGSV,3,3,10,22,39,053,48,28,15,320,*77
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$GPRMC,141915.00,A,4545.6423,N,00306.6039,E,0.6,110.2,010206,,*31
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$GPGLL,4545.6423,N,00306.6039,E,141915.00,A*07
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$GPGGA,141915.00,4545.0242,N,00306.6039,E,1,05,3.4,499.5,M,,M,,*75
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$GPGSA,A,3,,03,,22,14,,01,,18,,,,3.9,3.4,1.9*39
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$GPVTG,110.2,T,,M,0.6,N,1.2,K*67
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$GPZDA,141915.00,01,02,2006,00,00*68
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$GPGSV,3,1,10,01,13,142,45,03,48,144,47,11,41,277,,14,27,104,41*75
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$GPGSV,3,2,10,15,03,077,,18,04,041,42,19,85,271,,20,08,214,*7C
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$GPGSV,3,3,10,22,39,053,49,28,15,320,*76
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$GPRMC,141916.00,A,4545.6422,N,00306.6037,E,0.1,211.1,010206,,*3B
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$GPGLL,4545.6422,N,00306.6037,E,141916.00,A*0B
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$GPGGA,141916.00,4545.0484,N,00306.6037,E,1,05,3.4,500.0,M,,M,,*70
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$GPGSA,A,3,,03,,22,14,,01,,18,,,,3.9,3.4,1.9*39
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$GPVTG,211.1,T,,M,0.1,N,0.2,K*60
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$GPZDA,141916.00,01,02,2006,00,00*6B
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$GPGSV,3,1,10,01,13,142,45,03,48,144,48,11,41,277,,14,27,104,43*78
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$GPGSV,3,2,10,15,03,077,,18,04,041,44,19,85,271,,20,08,214,*7A
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$GPGSV,3,3,10,22,39,053,48,28,15,320,*77
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$GPRMC,141917.00,A,4545.6422,N,00306.6039,E,0.3,122.3,010206,,*37
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$GPGLL,4545.6422,N,00306.6039,E,141917.00,A*04
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$GPGGA,141917.00,4545.0726,N,00306.6039,E,1,05,3.4,499.6,M,,M,,*73
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$GPGSA,A,3,,03,,22,14,,01,,18,,,,3.9,3.4,1.9*39
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$GPVTG,122.3,T,,M,0.3,N,0.5,K*64
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$GPZDA,141917.00,01,02,2006,00,00*6A
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$GPGSV,3,1,10,01,13,142,45,03,48,144,46,11,41,277,,14,27,104,41*74
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$GPGSV,3,2,10,15,03,077,,18,04,041,42,19,85,271,,20,08,214,*7C
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$GPGSV,3,3,10,22,39,053,48,28,15,320,*77
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$GPRMC,141918.00,A,4545.6421,N,00306.6034,E,0.5,252.2,010206,,*35
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$GPGLL,4545.6421,N,00306.6034,E,141918.00,A*05
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$GPGGA,141918.00,4545.0968,N,00306.6034,E,1,05,3.4,498.8,M,,M,,*7A
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$GPGSA,A,3,,03,,22,14,,01,,18,,,,3.9,3.4,1.9*39
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$GPVTG,252.2,T,,M,0.5,N,1.0,K*63
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$GPZDA,141918.00,01,02,2006,00,00*65
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$GPGSV,3,1,10,01,13,142,45,03,48,144,48,11,41,277,,14,27,104,42*79
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$GPGSV,3,2,10,15,03,077,,18,04,041,42,19,85,271,,20,08,214,*7C
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$GPGSV,3,3,10,22,38,053,49,28,15,320,*77
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$GPRMC,141919.00,A,4545.6420,N,00306.6040,E,0.6,95.2,010206,,*0C
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$GPGLL,4545.6420,N,00306.6040,E,141919.00,A*06
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$GPGGA,141919.00,4545.1210,N,00306.6040,E,1,05,3.4,500.2,M,,M,,*77
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$GPGSA,A,3,,03,,22,14,,01,,18,,,,3.9,3.4,1.9*39
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$GPVTG,95.2,T,,M,0.6,N,1.2,K*5B
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$GPZDA,141919.00,01,02,2006,00,00*64
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$GPGSV,3,1,10,01,13,142,46,03,48,144,49,11,41,277,,14,27,104,42*7B
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$GPGSV,3,2,10,15,03,077,,18,04,041,43,19,85,271,,20,08,214,*7D
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$GPGSV,3,3,10,22,38,053,49,28,15,320,*77
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$GPRMC,141920.00,A,4545.6419,N,00306.6039,E,0.2,133.1,010206,,*38
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$GPGLL,4545.6419,N,00306.6039,E,141920.00,A*08
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$GPGGA,141920.00,4545.1410,N,00306.6039,E,1,05,3.4,500.0,M,,M,,*77
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$GPGSA,A,3,,03,,22,14,,01,,18,,,,3.9,3.4,1.9*39
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$GPVTG,133.1,T,,M,0.2,N,0.4,K*66
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$GPZDA,141920.00,01,02,2006,00,00*6E
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$GPGSV,3,1,10,01,13,142,45,03,48,144,46,11,41,277,,14,27,104,43*76
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$GPGSV,3,2,10,15,03,077,,18,04,041,41,19,85,271,,20,08,214,*7F
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$GPGSV,3,3,10,22,38,053,50,28,15,320,*7F
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$GPRMC,141921.00,A,4545.6419,N,00306.6043,E,0.6,103.1,010206,,*33
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$GPGLL,4545.6419,N,00306.6043,E,141921.00,A*04
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$GPGGA,141921.00,4545.1610,N,00306.6043,E,1,05,3.4,499.8,M,,M,,*70
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$GPGSA,A,3,,03,,22,14,,01,,18,,,,3.9,3.4,1.9*39
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$GPVTG,103.1,T,,M,0.6,N,1.1,K*65
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$GPZDA,141921.00,01,02,2006,00,00*6F
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$GPGSV,3,1,10,01,13,142,46,03,48,144,48,11,41,277,,14,27,104,42*7A
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$GPGSV,3,2,10,15,03,077,,18,04,041,42,19,85,271,,20,08,214,*7C
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$GPGSV,3,3,10,22,38,053,48,28,15,320,*76
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$GPRMC,141922.00,A,4545.6418,N,00306.6046,E,0.7,96.9,010206,,*00
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$GPGLL,4545.6418,N,00306.6046,E,141922.00,A*03
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$GPGGA,141922.00,4545.1810,N,00306.6046,E,1,05,3.4,500.6,M,,M,,*77
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$GPGSA,A,3,,03,,22,14,,01,,18,,,,3.9,3.4,1.9*39
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$GPVTG,96.9,T,,M,0.7,N,1.3,K*53
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$GPZDA,141922.00,01,02,2006,00,00*6C
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$GPGSV,3,1,10,01,13,142,47,03,48,144,46,11,41,277,,14,27,104,43*74
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$GPGSV,3,2,10,15,03,077,,18,04,041,43,19,85,271,,20,08,214,*7D
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$GPGSV,3,3,10,22,38,053,48,28,15,320,*76
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$GPRMC,141923.00,A,4545.6417,N,00306.6046,E,0.3,113.6,010206,,*39
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$GPGLL,4545.6417,N,00306.6046,E,141923.00,A*0D
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$GPGGA,141923.00,4545.2010,N,00306.6046,E,1,05,3.4,500.6,M,,M,,*7D
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$GPGSA,A,3,,03,,22,14,,01,,18,,,,3.9,3.4,1.9*39
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$GPVTG,113.6,T,,M,0.3,N,0.7,K*61
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$GPZDA,141923.00,01,02,2006,00,00*6D
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$GPGSV,3,1,10,01,13,142,45,03,48,144,47,11,41,277,,14,27,104,41*75
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$GPGSV,3,2,10,15,03,077,,18,04,041,43,19,85,271,,20,08,214,*7D
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$GPGSV,3,3,10,22,38,053,49,28,15,320,*77
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$GPRMC,141924.00,A,4545.6416,N,00306.6044,E,0.2,197.7,010206,,*31
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$GPGLL,4545.6416,N,00306.6044,E,141924.00,A*09
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$GPGGA,141924.00,4545.2210,N,00306.6044,E,1,05,3.4,500.5,M,,M,,*79
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$GPGSA,A,3,,03,,22,14,,01,,18,,,,3.9,3.4,1.9*39
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$GPVTG,197.7,T,,M,0.2,N,0.4,K*6E
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$GPZDA,141924.00,01,02,2006,00,00*6A
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$GPGSV,3,1,10,01,13,142,45,03,48,144,47,11,41,277,,14,27,104,40*74
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$GPGSV,3,2,10,15,03,077,,18,04,041,43,19,85,271,,20,08,214,*7D
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$GPGSV,3,3,10,22,38,053,49,28,15,320,*77
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$GPRMC,141925.00,A,4545.6415,N,00306.6046,E,0.2,130.8,010206,,*33
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$GPGLL,4545.6415,N,00306.6046,E,141925.00,A*09
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$GPGGA,141925.00,4545.2410,N,00306.6046,E,1,05,3.4,501.4,M,,M,,*7C
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$GPGSA,A,3,,03,,22,14,,01,,18,,,,3.9,3.4,1.9*39
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$GPVTG,130.8,T,,M,0.2,N,0.5,K*6D
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$GPZDA,141925.00,01,02,2006,00,00*6B
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$GPGSV,3,1,10,01,13,142,45,03,48,144,47,11,41,277,,14,27,104,40*74
|
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$GPGSV,3,2,10,15,03,077,,18,04,041,41,19,85,271,,20,08,214,*7F
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$GPGSV,3,3,10,22,38,053,47,28,15,320,*79
|
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$GPRMC,141926.?E,0.2,260.8,010206,,*34
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| branch/DEMAGALHAES/sp4a12/trame.c | ||
|---|---|---|
|
/* Fichier trames.c - Gestion et decodage des trames */
|
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/* Ce fichier sera fourni */
|
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|
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#include <stdio.h>
|
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#include <stdlib.h>
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#include "trame.h"
|
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|
|
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#define FICHIER_TRAMES "gps.log" /* Par exemple */
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|
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#define MAX_FRAME_LENGTH 80
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static char trame_buf[MAX_FRAME_LENGTH];
|
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static FILE *trame_fic;
|
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|
|
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int trame_init(void)
|
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|
{
|
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|
trame_fic = fopen(FICHIER_TRAMES, "r");
|
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|
if (trame_fic)
|
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return 1;
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|
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fprintf(stderr, "Impossible d'ouvrir le fichier %s\n", FICHIER_TRAMES);
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return 0;
|
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}
|
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|
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char *trame_suivante(void)
|
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|
{
|
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|
return fgets(trame_buf, MAX_FRAME_LENGTH-1, trame_fic);
|
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|
}
|
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| branch/DEMAGALHAES/sp4a12/sp4a.cbp | ||
|---|---|---|
|
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
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|
<CodeBlocks_project_file>
|
||
|
<FileVersion major="1" minor="6" />
|
||
|
<Project>
|
||
|
<Option title="sp4a" />
|
||
|
<Option pch_mode="2" />
|
||
|
<Option compiler="gcc" />
|
||
|
<Build>
|
||
|
<Target title="Debug">
|
||
|
<Option output="sp4a" prefix_auto="1" extension_auto="1" />
|
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|
<Option object_output=".\debug" />
|
||
|
<Option type="1" />
|
||
|
<Option compiler="gcc" />
|
||
|
<Compiler>
|
||
|
<Add option="-g" />
|
||
|
</Compiler>
|
||
|
</Target>
|
||
|
</Build>
|
||
|
<Compiler>
|
||
|
<Add option="-Wall" />
|
||
|
</Compiler>
|
||
|
<Unit filename="gps.log" />
|
||
|
<Unit filename="main.c">
|
||
|
<Option compilerVar="CC" />
|
||
|
</Unit>
|
||
|
<Unit filename="trame.c">
|
||
|
<Option compilerVar="CC" />
|
||
|
</Unit>
|
||
|
<Unit filename="trame.h" />
|
||
|
<Extensions>
|
||
|
<code_completion />
|
||
|
<envvars />
|
||
|
<debugger />
|
||
|
<lib_finder disable_auto="1" />
|
||
|
</Extensions>
|
||
|
</Project>
|
||
|
</CodeBlocks_project_file>
|
||
| branch/DEMAGALHAES/sp4a12/trame.h | ||
|---|---|---|
|
|
||
|
int trame_init(void);
|
||
|
char * trame_suivante(void);
|
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| branch/DEMAGALHAES/sfr32c87.h | ||
|---|---|---|
|
/************************************************************************************
|
||
|
* *
|
||
|
* File name : sfr32c87.h *
|
||
|
* Contents : Definition of M32C/87 Group SFR *
|
||
|
* *
|
||
|
* Copyright, 2003 RENESAS TECHNOLOGY CORPORATION *
|
||
|
* AND RENESAS SOLUTIONS CORPORATION *
|
||
|
* *
|
||
|
* Note : *
|
||
|
* *
|
||
|
* Version : Ver 0.01 (04-09-23) Preliminary *
|
||
|
* These data made based on M32C/85 Group H/W Manual Rev.0.30 *
|
||
|
* Version : Ver 0.02 (04-12-02) Preliminary *
|
||
|
* Version : Ver 0.03 (04-12-22) Preliminary *
|
||
|
* Version : Ver 0.04 (05-12-08) Preliminary *
|
||
|
* Version : Ver 0.05 (06-01-23) Preliminary *
|
||
|
* *
|
||
|
*************************************************************************************/
|
||
|
/*
|
||
|
note:
|
||
|
This data is a freeware that SFR for M32C/87 group are described.
|
||
|
RENESAS TECHNOLOGY CORPORATION and RENESAS SOLUTIONS CORPORATION assume
|
||
|
no responsibility for any damage that occurred by this data.
|
||
|
*/
|
||
|
|
||
|
/************************************************************************
|
||
|
* declare SFR address *
|
||
|
************************************************************************/
|
||
|
#pragma ADDRESS pm0_addr 0004H /* Processor mode register 0 */
|
||
|
#pragma ADDRESS pm1_addr 0005H /* Processor mode register 1 */
|
||
|
#pragma ADDRESS cm0_addr 0006H /* System clock control register 0 */
|
||
|
#pragma ADDRESS cm1_addr 0007H /* System clock control register 1 */
|
||
|
|
||
|
#pragma ADDRESS aier_addr 0009H /* Address match interrupt enable register */
|
||
|
#pragma ADDRESS prcr_addr 000aH /* Protect register */
|
||
|
#pragma ADDRESS ds_addr 000bH /* External data bus width control register */
|
||
|
#pragma ADDRESS mcd_addr 000cH /* Main clock division register */
|
||
|
#pragma ADDRESS cm2_addr 000dH /* Oscillation stop detect register */
|
||
|
#pragma ADDRESS wdts_addr 000eH /* Watchdog timer start register */
|
||
|
#pragma ADDRESS wdc_addr 000fH /* Watchdog timer control register */
|
||
|
#pragma ADDRESS rmad0_addr 0010H /* Address match interrupt register 0 */
|
||
|
#pragma ADDRESS pm2_addr 0013H /* Processor mode register 2 */
|
||
|
#pragma ADDRESS rmad1_addr 0014H /* Address match interrupt register 1 */
|
||
|
#pragma ADDRESS vcr2_addr 0017H /* Voltage detection register 2 */
|
||
|
#pragma ADDRESS rmad2_addr 0018H /* Address match interrupt register 2 */
|
||
|
#pragma ADDRESS vcr1_addr 001bH /* Voltage detection register 1 */
|
||
|
#pragma ADDRESS rmad3_addr 001cH /* Address match interrupt register 3 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS plc_addr 0026H /* PLL control register */
|
||
|
#pragma ADDRESS plc0_addr 0026H /* PLL control register 0 */
|
||
|
#pragma ADDRESS plc1_addr 0027H /* PLL control register 1 */
|
||
|
#pragma ADDRESS rmad4_addr 0028H /* Address match interrupt register 4 */
|
||
|
|
||
|
#pragma ADDRESS rmad5_addr 002CH /* Address match interrupt register 5 */
|
||
|
#pragma ADDRESS d4int_addr 002FH /* Voltage down detect interrupt register */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS rmad6_addr 0038H /* Address match interrupt register 6 */
|
||
|
#pragma ADDRESS rmad7_addr 003CH /* Address match interrupt register 7 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS ewcr0_addr 0048H /* External space wait control register 0 */
|
||
|
#pragma ADDRESS ewcr1_addr 0049H /* External space wait control register 1 */
|
||
|
#pragma ADDRESS ewcr2_addr 004AH /* External space wait control register 2 */
|
||
|
#pragma ADDRESS ewcr3_addr 004BH /* External space wait control register 3 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS fmr1_addr 0055H /* Flash Memory Control Register 1 */
|
||
|
|
||
|
#pragma ADDRESS fmr_addr 0057H /* Flash memory control register 0 */
|
||
|
#pragma ADDRESS fmr0_addr 0057H /* Flash memory control register 0 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS dm0ic_addr 0068H /* DMA0 interrupt control register */
|
||
|
#pragma ADDRESS tb5ic_addr 0069H /* Timer B5 interrupt register */
|
||
|
#pragma ADDRESS dm2ic_addr 006aH /* DMA2 interrupt register */
|
||
|
#pragma ADDRESS s2ric_addr 006bH /* UART2 receive/ack interrupt control register */
|
||
|
#pragma ADDRESS ta0ic_addr 006cH /* Timer A0 interrupt control register */
|
||
|
#pragma ADDRESS s3ric_addr 006dH /* UART3 receive/ack interrupt control register */
|
||
|
#pragma ADDRESS ta2ic_addr 006eH /* Timer A2 interrupt control register */
|
||
|
#pragma ADDRESS s4ric_addr 006fH /* UART4 receive/ack interrupt control register */
|
||
|
#pragma ADDRESS ta4ic_addr 0070H /* Timer A4 interrupt control register */
|
||
|
#pragma ADDRESS bcn0ic_addr 0071H /* Bus collision (UART0) interrupt control register */
|
||
|
#pragma ADDRESS bcn3ic_addr 0071H /* Bus collision (UART3) interrupt control register */
|
||
|
#pragma ADDRESS s0ric_addr 0072H /* UART0 receive interrupt control register */
|
||
|
#pragma ADDRESS ad0ic_addr 0073H /* A/D0 conversion interrupt control register */
|
||
|
#pragma ADDRESS s1ric_addr 0074H /* UART1 receive interrupt control register */
|
||
|
#pragma ADDRESS iio0ic_addr 0075H /* Intelligent I/O interrupt control register 0 */
|
||
|
#pragma ADDRESS can3ic_addr 0075H /* CAN interrupt 3 control register */
|
||
|
#pragma ADDRESS tb1ic_addr 0076H /* Timer B1 interrupt control register */
|
||
|
#pragma ADDRESS iio2ic_addr 0077H /* Intelligent I/O interrupt control register 2 */
|
||
|
#pragma ADDRESS tb3ic_addr 0078H /* Timer B3 interrupt control register */
|
||
|
#pragma ADDRESS iio4ic_addr 0079H /* Intelligent I/O interrupt control register 4 */
|
||
|
#pragma ADDRESS int5ic_addr 007aH /* INT5~ interrupt control register */
|
||
|
#pragma ADDRESS iio6ic_addr 007bH /* Intelligent I/O interrupt control register 6 */
|
||
|
#pragma ADDRESS int3ic_addr 007cH /* INT3~ interrupt control register */
|
||
|
#pragma ADDRESS iio8ic_addr 007dH /* Intelligent I/O interrupt control register 8 */
|
||
|
#pragma ADDRESS int1ic_addr 007eH /* INT1~ interrupt control register */
|
||
|
#pragma ADDRESS iio10ic_addr 007fH /* Intelligent I/O interrupt control register 10 */
|
||
|
#pragma ADDRESS can1ic_addr 007fH /* CAN Interrupt 1 Control Register */
|
||
|
|
||
|
#pragma ADDRESS iio11ic_addr 0081H /* Intelligent I/O interrupt control register 11 */
|
||
|
#pragma ADDRESS can2ic_addr 0081H /* CAN Interrupt 2 Control Register */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS dm1ic_addr 0088H /* DMA1 interrupt control register */
|
||
|
#pragma ADDRESS s2tic_addr 0089H /* UART2 transmit/nack interrupt control register */
|
||
|
#pragma ADDRESS dm3ic_addr 008aH /* DMA3 interrupt control register */
|
||
|
#pragma ADDRESS s3tic_addr 008bH /* UART3 transmit/nack interrupt control register */
|
||
|
#pragma ADDRESS ta1ic_addr 008cH /* Timer A1 interrupt control register */
|
||
|
#pragma ADDRESS s4tic_addr 008dH /* UART4 transmit/nack interrupt control register */
|
||
|
#pragma ADDRESS ta3ic_addr 008eH /* Timer A3 interrupt control register */
|
||
|
#pragma ADDRESS bcn2ic_addr 008fH /* Bus collision (UART2) interrupt control register */
|
||
|
#pragma ADDRESS s0tic_addr 0090H /* UART0 transmit interrupt control register */
|
||
|
#pragma ADDRESS bcn1ic_addr 0091H /* Bus collision (UART1) interrupt control register*/
|
||
|
#pragma ADDRESS bcn4ic_addr 0091H /* Bus collision (UART4) interrupt control register */
|
||
|
#pragma ADDRESS s1tic_addr 0092H /* UART1 transmit interrupt control register */
|
||
|
#pragma ADDRESS kupic_addr 0093H /* Key input interrupt control register */
|
||
|
#pragma ADDRESS tb0ic_addr 0094H /* Timer B0 interrupt control register */
|
||
|
#pragma ADDRESS iio1ic_addr 0095H /* Intelligent I/O interrupt control register 1 */
|
||
|
#pragma ADDRESS can4ic_addr 0095H /* CAN Interrupt 4 Control Register */
|
||
|
#pragma ADDRESS tb2ic_addr 0096H /* Timer B2 interrupt control register */
|
||
|
#pragma ADDRESS iio3ic_addr 0097H /* Intelligent I/O interrupt control register 3 */
|
||
|
#pragma ADDRESS tb4ic_addr 0098H /* Timer B4 interrupt control register */
|
||
|
#pragma ADDRESS iio5ic_addr 0099H /* Intelligent I/O interrupt control register 5 */
|
||
|
#pragma ADDRESS can5ic_addr 0099H /* CAN Interrupt 5 Control Register */
|
||
|
#pragma ADDRESS int4ic_addr 009aH /* INT4~ interrupt control register */
|
||
|
#pragma ADDRESS iio7ic_addr 009bH /* Intelligent I/O interrupt control register 7 */
|
||
|
#pragma ADDRESS int2ic_addr 009cH /* INT2~ interrupt control register */
|
||
|
#pragma ADDRESS iio9ic_addr 009dH /* Intelligent I/O interrupt control register 9 */
|
||
|
#pragma ADDRESS can0ic_addr 009dH /* CAN0 Interrupt Control Register*/
|
||
|
#pragma ADDRESS int0ic_addr 009eH /* INT0~ interrupt control register */
|
||
|
#pragma ADDRESS rlvl_addr 009fH /* Exit priority register */
|
||
|
#pragma ADDRESS iio0ir_addr 00a0H /* Interrupt request register 0 */
|
||
|
#pragma ADDRESS iio1ir_addr 00a1H /* Interrupt request register 1 */
|
||
|
#pragma ADDRESS iio2ir_addr 00a2H /* Interrupt request register 2 */
|
||
|
#pragma ADDRESS iio3ir_addr 00a3H /* Interrupt request register 3 */
|
||
|
#pragma ADDRESS iio4ir_addr 00a4H /* Interrupt request register 4 */
|
||
|
#pragma ADDRESS iio5ir_addr 00a5H /* Interrupt request register 5 */
|
||
|
#pragma ADDRESS iio6ir_addr 00a6H /* Interrupt request register 6 */
|
||
|
#pragma ADDRESS iio7ir_addr 00a7H /* Interrupt request register 7 */
|
||
|
#pragma ADDRESS iio8ir_addr 00a8H /* Interrupt request register 8 */
|
||
|
#pragma ADDRESS iio9ir_addr 00a9H /* Interrupt request register 9 */
|
||
|
#pragma ADDRESS iio10ir_addr 00aaH /* Interrupt request register 10 */
|
||
|
#pragma ADDRESS iio11ir_addr 00abH /* Interrupt request register 11 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS iio0ie_addr 00b0H /* Interrupt enable register 0 */
|
||
|
#pragma ADDRESS iio1ie_addr 00b1H /* Interrupt enable register 1 */
|
||
|
#pragma ADDRESS iio2ie_addr 00b2H /* Interrupt enable register 2 */
|
||
|
#pragma ADDRESS iio3ie_addr 00b3H /* Interrupt enable register 3 */
|
||
|
#pragma ADDRESS iio4ie_addr 00b4H /* Interrupt enable register 4 */
|
||
|
#pragma ADDRESS iio5ie_addr 00b5H /* Interrupt enable register 5 */
|
||
|
#pragma ADDRESS iio6ie_addr 00b6H /* Interrupt enable register 6 */
|
||
|
#pragma ADDRESS iio7ie_addr 00b7H /* Interrupt enable register 7 */
|
||
|
#pragma ADDRESS iio8ie_addr 00b8H /* Interrupt enable register 8 */
|
||
|
#pragma ADDRESS iio9ie_addr 00b9H /* Interrupt enable register 9 */
|
||
|
#pragma ADDRESS iio10ie_addr 00baH /* Interrupt enable register 10 */
|
||
|
#pragma ADDRESS iio11ie_addr 00bbH /* Interrupt enable register 11 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS g0rb_addr 00e8H /* SI/O receive buffer register 0 */
|
||
|
#pragma ADDRESS g0tb_addr 00eaH /* Transmit buffer register 0 */
|
||
|
#pragma ADDRESS g0dr_addr 00eaH /* Receive data register 0 */
|
||
|
|
||
|
#pragma ADDRESS g0ri_addr 00ecH /* Receive input register 0 */
|
||
|
#pragma ADDRESS g0mr_addr 00edH /* SI/O communication control register 0 */
|
||
|
#pragma ADDRESS g0to_addr 00eeH /* Transmit output register 0 */
|
||
|
#pragma ADDRESS g0cr_addr 00efH /* SI/O communication control register 0 */
|
||
|
#pragma ADDRESS g0cmp0_addr 00f0H /* Data compare register 00 */
|
||
|
#pragma ADDRESS g0cmp1_addr 00f1H /* Data compare register 01 */
|
||
|
#pragma ADDRESS g0cmp2_addr 00f2H /* Data compare register 02 */
|
||
|
#pragma ADDRESS g0cmp3_addr 00f3H /* Data compare register 03 */
|
||
|
#pragma ADDRESS g0msk0_addr 00f4H /* Data mask register 00 */
|
||
|
#pragma ADDRESS g0msk1_addr 00f5H /* Data mask register 01 */
|
||
|
#pragma ADDRESS ccs_addr 00f6H /* Communication clock select register */
|
||
|
|
||
|
#pragma ADDRESS g0rcrc_addr 00f8H /* Receive CRC code register 0 */
|
||
|
#pragma ADDRESS g0tcrc_addr 00faH /* Transmit CRC code register 0 */
|
||
|
#pragma ADDRESS g0emr_addr 00fcH /* SI/O expansion mode register 0 */
|
||
|
#pragma ADDRESS g0erc_addr 00fdH /* SI/O expansion receive control register 0 */
|
||
|
#pragma ADDRESS g0irf_addr 00feH /* SI/O special communication interrupt detect register 0 */
|
||
|
#pragma ADDRESS g0etc_addr 00ffH /* SI/O expansion transmit control register 0 */
|
||
|
#pragma ADDRESS g1tm0_addr 0100H /* Time measurement register 10 */
|
||
|
#pragma ADDRESS g1po0_addr 0100H /* Waveform generate register 10 */
|
||
|
#pragma ADDRESS g1tm1_addr 0102H /* Time measurement register 11 */
|
||
|
#pragma ADDRESS g1po1_addr 0102H /* Waveform generate register 11 */
|
||
|
#pragma ADDRESS g1tm2_addr 0104H /* Time measurement register 12 */
|
||
|
#pragma ADDRESS g1po2_addr 0104H /* Waveform generate register 12 */
|
||
|
#pragma ADDRESS g1tm3_addr 0106H /* Time measurement register 13 */
|
||
|
#pragma ADDRESS g1po3_addr 0106H /* Waveform generate register 13 */
|
||
|
#pragma ADDRESS g1tm4_addr 0108H /* Time measurement register 14 */
|
||
|
#pragma ADDRESS g1po4_addr 0108H /* Waveform generate register 14 */
|
||
|
#pragma ADDRESS g1tm5_addr 010aH /* Time measurement register 15 */
|
||
|
#pragma ADDRESS g1po5_addr 010aH /* Waveform generate register 15 */
|
||
|
#pragma ADDRESS g1tm6_addr 010cH /* Time measurement register 16 */
|
||
|
#pragma ADDRESS g1po6_addr 010cH /* Waveform generate register 16 */
|
||
|
#pragma ADDRESS g1tm7_addr 010eH /* Time measurement register 17 */
|
||
|
#pragma ADDRESS g1po7_addr 010eH /* Waveform generate register 17 */
|
||
|
#pragma ADDRESS g1pocr0_addr 0110H /* Waveform generate control register 10 */
|
||
|
#pragma ADDRESS g1pocr1_addr 0111H /* Waveform generate control register 11 */
|
||
|
#pragma ADDRESS g1pocr2_addr 0112H /* Waveform generate control register 12 */
|
||
|
#pragma ADDRESS g1pocr3_addr 0113H /* Waveform generate control register 13 */
|
||
|
#pragma ADDRESS g1pocr4_addr 0114H /* Waveform generate control register 14 */
|
||
|
#pragma ADDRESS g1pocr5_addr 0115H /* Waveform generate control register 15 */
|
||
|
#pragma ADDRESS g1pocr6_addr 0116H /* Waveform generate control register 16 */
|
||
|
#pragma ADDRESS g1pocr7_addr 0117H /* Waveform generate control register 17 */
|
||
|
#pragma ADDRESS g1tmcr0_addr 0118H /* Time measurement control register 10 */
|
||
|
#pragma ADDRESS g1tmcr1_addr 0119H /* Time measurement control register 11 */
|
||
|
#pragma ADDRESS g1tmcr2_addr 011aH /* Time measurement control register 12 */
|
||
|
#pragma ADDRESS g1tmcr3_addr 011bH /* Time measurement control register 13 */
|
||
|
#pragma ADDRESS g1tmcr4_addr 011cH /* Time measurement control register 14 */
|
||
|
#pragma ADDRESS g1tmcr5_addr 011dH /* Time measurement control register 15 */
|
||
|
#pragma ADDRESS g1tmcr6_addr 011eH /* Time measurement control register 16 */
|
||
|
#pragma ADDRESS g1tmcr7_addr 011fH /* Time measurement control register 17 */
|
||
|
#pragma ADDRESS g1bt_addr 0120H /* Base timer register 1 */
|
||
|
#pragma ADDRESS g1bcr0_addr 0122H /* Base timer control register 10 */
|
||
|
#pragma ADDRESS g1bcr1_addr 0123H /* Base timer control register 11 */
|
||
|
#pragma ADDRESS g1tpr6_addr 0124H /* Time measurement prescaler register 16 */
|
||
|
#pragma ADDRESS g1tpr7_addr 0125H /* Time measurement prescaler register 17 */
|
||
|
#pragma ADDRESS g1fe_addr 0126H /* Function enable register 1 */
|
||
|
#pragma ADDRESS g1fs_addr 0127H /* Function select register 1 */
|
||
|
#pragma ADDRESS g1rb_addr 0128H /* SI/O receive buffer register 1 */
|
||
|
#pragma ADDRESS g1tb_addr 012aH /* Transmit buffer register 1 */
|
||
|
#pragma ADDRESS g1dr_addr 012aH /* Receive data register 1 */
|
||
|
|
||
|
#pragma ADDRESS g1ri_addr 012cH /* Receive input register 1 */
|
||
|
#pragma ADDRESS g1mr_addr 012dH /* SI/O communication mode register 1 */
|
||
|
#pragma ADDRESS g1to_addr 012eH /* Transmit output register 1 */
|
||
|
#pragma ADDRESS g1cr_addr 012fH /* SI/O communication control register 1 */
|
||
|
#pragma ADDRESS g1cmp0_addr 0130H /* Data compare register 10 */
|
||
|
#pragma ADDRESS g1cmp1_addr 0131H /* Data compare register 11 */
|
||
|
#pragma ADDRESS g1cmp2_addr 0132H /* Data compare register 12 */
|
||
|
#pragma ADDRESS g1cmp3_addr 0133H /* Data compare register 13 */
|
||
|
#pragma ADDRESS g1msk0_addr 0134H /* Data mask register 10 */
|
||
|
#pragma ADDRESS g1msk1_addr 0135H /* Data mask register 11 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS g1rcrc_addr 0138H /* Receive CRC code register 1 */
|
||
|
#pragma ADDRESS g1tcrc_addr 013aH /* Transmit CRC code register 1 */
|
||
|
#pragma ADDRESS g1emr_addr 013cH /* SI/O extended mode register 1 */
|
||
|
#pragma ADDRESS g1erc_addr 013dH /* SI/O extended receive control register 1 */
|
||
|
#pragma ADDRESS g1irf_addr 013eH /* SI/O special communication interrupt detect register 1 */
|
||
|
#pragma ADDRESS g1etc_addr 013fH /* SI/O extended transmit control register 1 */
|
||
|
|
||
|
#pragma ADDRESS g2po0_addr 0140H
|
||
|
#pragma ADDRESS g2po1_addr 0142H
|
||
|
#pragma ADDRESS g2po2_addr 0144H
|
||
|
#pragma ADDRESS g2po3_addr 0146H
|
||
|
#pragma ADDRESS g2po4_addr 0148H
|
||
|
#pragma ADDRESS g2po5_addr 014aH
|
||
|
#pragma ADDRESS g2po6_addr 014cH
|
||
|
#pragma ADDRESS g2po7_addr 014eH
|
||
|
#pragma ADDRESS g2pocr0_addr 0150H
|
||
|
#pragma ADDRESS g2pocr1_addr 0151H
|
||
|
#pragma ADDRESS g2pocr2_addr 0152H
|
||
|
#pragma ADDRESS g2pocr3_addr 0153H
|
||
|
#pragma ADDRESS g2pocr4_addr 0154H
|
||
|
#pragma ADDRESS g2pocr5_addr 0155H
|
||
|
#pragma ADDRESS g2pocr6_addr 0156H
|
||
|
#pragma ADDRESS g2pocr7_addr 0157H
|
||
|
|
||
|
|
||
|
#pragma ADDRESS g2bt_addr 0160H
|
||
|
#pragma ADDRESS g2bcr0_addr 0162H
|
||
|
#pragma ADDRESS g2bcr1_addr 0163H
|
||
|
#pragma ADDRESS btsr_addr 0164H
|
||
|
|
||
|
#pragma ADDRESS g2fe_addr 0166H
|
||
|
#pragma ADDRESS g2rtp_addr 0167H
|
||
|
|
||
|
|
||
|
#pragma ADDRESS g2mr_addr 016aH
|
||
|
#pragma ADDRESS g2cr_addr 016bH
|
||
|
#pragma ADDRESS g2tb_addr 016cH
|
||
|
#pragma ADDRESS g2rb_addr 016eH
|
||
|
#pragma ADDRESS iear_addr 0170H
|
||
|
#pragma ADDRESS iecr_addr 0172H
|
||
|
#pragma ADDRESS ietif_addr 0173H
|
||
|
#pragma ADDRESS ierif_addr 0174H
|
||
|
|
||
|
|
||
|
#pragma ADDRESS ipsb_addr 0177H /* Input function select register B */
|
||
|
#pragma ADDRESS ips_addr 0178H /* Input function select register */
|
||
|
#pragma ADDRESS ipsa_addr 0179H /* Input function select register A */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS u5mr_addr 01c0H /* UART5 transmit/receive mode register */
|
||
|
#pragma ADDRESS u5brg_addr 01c1H /* UART5 bit rate generator */
|
||
|
#pragma ADDRESS u5tb_addr 01c2H /* UART5 transmit buffer register */
|
||
|
#pragma ADDRESS u5c0_addr 01c4H /* UART5 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u5c1_addr 01c5H /* UART5 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u5rb_addr 01c6H /* UART5 receive buffer register */
|
||
|
#pragma ADDRESS u6mr_addr 01c8H /* UART6 transmit/receive mode register */
|
||
|
#pragma ADDRESS u6brg_addr 01c9H /* UART6 bit rate generator */
|
||
|
#pragma ADDRESS u6tb_addr 01caH /* UART6 transmit buffer register */
|
||
|
#pragma ADDRESS u6c0_addr 01ccH /* UART6 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u6c1_addr 01cdH /* UART6 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u6rb_addr 01ceH /* UART6 receive buffer register */
|
||
|
#pragma ADDRESS u56con_addr 01d0H
|
||
|
#pragma ADDRESS u56is_addr 01d1H
|
||
|
|
||
|
|
||
|
#pragma ADDRESS rtp0r_addr 01d8H
|
||
|
#pragma ADDRESS rtp1r_addr 01d9H
|
||
|
#pragma ADDRESS rtp2r_addr 01daH
|
||
|
#pragma ADDRESS rtp3r_addr 01dbH
|
||
|
|
||
|
|
||
|
|
||
|
/************************************************************************
|
||
|
* CAN 0 SFR Address area *
|
||
|
************************************************************************/
|
||
|
#pragma ADDRESS c0slot 01e0H /* CAN0 Message Slot Buffer */
|
||
|
#pragma ADDRESS c0slot0 01e0H /* CAN0 Message Slot Buffer 0 */
|
||
|
#pragma ADDRESS c0slot1 01f0H /* CAN0 Message Slot Buffer 1 */
|
||
|
#pragma ADDRESS c0ctlr0_addr 0200H /* CAN0 Control Register 0 */
|
||
|
#pragma ADDRESS c0str_addr 0202H /* CAN0 Status Register */
|
||
|
#pragma ADDRESS c0idr_addr 0204H /* CAN0 Extended ID Register */
|
||
|
#pragma ADDRESS c0conr_addr 0206H /* CAN0 Configuration Register */
|
||
|
#pragma ADDRESS c0tsr_addr 0208H /* CAN0 Time Stamp Register */
|
||
|
#pragma ADDRESS c0tec_addr 020aH /* CAN0 Transmit Error Counter */
|
||
|
#pragma ADDRESS c0rec_addr 020bH /* CAN0 Receive Error Counter */
|
||
|
#pragma ADDRESS c0sistr_addr 020cH /* CAN0 Slot Interrupt Status Register */
|
||
|
#pragma ADDRESS c0simkr_addr 0210H /* CAN0 Slot Interrupt Mask Register */
|
||
|
#pragma ADDRESS c0eimkr_addr 0214H /* CAN0 Error Interrupt Mask Register */
|
||
|
#pragma ADDRESS c0eistr_addr 0215H /* CAN0 Error Interrupt Status Register */
|
||
|
#pragma ADDRESS c0efr_addr 0216H /* CAN0 Error Factor Register */
|
||
|
#pragma ADDRESS c0brp_addr 0217H /* CAN0 Baud Rate Prescaler */
|
||
|
#pragma ADDRESS c0mdr_addr 0219H /* CAN0 Mode Register */
|
||
|
#pragma ADDRESS c0ssctlr_addr 0220H /* (BANK0) CAN0 Single Shot Control Register */
|
||
|
#pragma ADDRESS c0ssstr_addr 0224H /* (BANK0) CAN0 Single Shot Status Register */
|
||
|
#pragma ADDRESS c0mctl 0230H /* (BANK0) CAN0 Message Control Register */
|
||
|
#pragma ADDRESS c0mctl0 0230H /* (BANK0) CAN0 Message Slot0 Control Register */
|
||
|
#pragma ADDRESS c0mctl1 0231H /* (BANK0) CAN0 Message Slot1 Control Register */
|
||
|
#pragma ADDRESS c0mctl2 0232H /* (BANK0) CAN0 Message Slot2 Control Register */
|
||
|
#pragma ADDRESS c0mctl3 0233H /* (BANK0) CAN0 Message Slot3 Control Register */
|
||
|
#pragma ADDRESS c0mctl4 0234H /* (BANK0) CAN0 Message Slot4 Control Register */
|
||
|
#pragma ADDRESS c0mctl5 0235H /* (BANK0) CAN0 Message Slot5 Control Register */
|
||
|
#pragma ADDRESS c0mctl6 0236H /* (BANK0) CAN0 Message Slot6 Control Register */
|
||
|
#pragma ADDRESS c0mctl7 0237H /* (BANK0) CAN0 Message Slot7 Control Register */
|
||
|
#pragma ADDRESS c0mctl8 0238H /* (BANK0) CAN0 Message Slot8 Control Register */
|
||
|
#pragma ADDRESS c0mctl9 0239H /* (BANK0) CAN0 Message Slot9 Control Register */
|
||
|
#pragma ADDRESS c0mctl10 023aH /* (BANK0) CAN0 Message Slot10 Control Register */
|
||
|
#pragma ADDRESS c0mctl11 023bH /* (BANK0) CAN0 Message Slot11 Control Register */
|
||
|
#pragma ADDRESS c0mctl12 023cH /* (BANK0) CAN0 Message Slot12 Control Register */
|
||
|
#pragma ADDRESS c0mctl13 023dH /* (BANK0) CAN0 Message Slot13 Control Register */
|
||
|
#pragma ADDRESS c0mctl14 023eH /* (BANK0) CAN0 Message Slot14 Control Register */
|
||
|
#pragma ADDRESS c0mctl15 023fH /* (BANK0) CAN0 Message Slot15 Control Register */
|
||
|
#pragma ADDRESS c0gmr 0228H /* (BANK1) CAN0 Global Mask Register */
|
||
|
#pragma ADDRESS c0gmr0_addr 0228H /* (BANK1) CAN0 Global Mask Register 0 */
|
||
|
#pragma ADDRESS c0gmr1_addr 0229H /* (BANK1) CAN0 Global Mask Register 1 */
|
||
|
#pragma ADDRESS c0gmr2_addr 022aH /* (BANK1) CAN0 Global Mask Register 2 */
|
||
|
#pragma ADDRESS c0gmr3_addr 022bH /* (BANK1) CAN0 Global Mask Register 3 */
|
||
|
#pragma ADDRESS c0gmr4_addr 022cH /* (BANK1) CAN0 Global Mask Register 4 */
|
||
|
#pragma ADDRESS c0lmar 0230H /* (BANK1) CAN0 Local Mask A Register */
|
||
|
#pragma ADDRESS c0lmar0_addr 0230H /* (BANK1) CAN0 Local Mask A Register 0 */
|
||
|
#pragma ADDRESS c0lmar1_addr 0231H /* (BANK1) CAN0 Local Mask A Register 1 */
|
||
|
#pragma ADDRESS c0lmar2_addr 0232H /* (BANK1) CAN0 Local Mask A Register 2 */
|
||
|
#pragma ADDRESS c0lmar3_addr 0233H /* (BANK1) CAN0 Local Mask A Register 3 */
|
||
|
#pragma ADDRESS c0lmar4_addr 0234H /* (BANK1) CAN0 Local Mask A Register 4 */
|
||
|
#pragma ADDRESS c0lmbr 0238H /* (BANK1) CAN0 Local Mask B Register */
|
||
|
#pragma ADDRESS c0lmbr0_addr 0238H /* (BANK1) CAN0 Local Mask B Register 0 */
|
||
|
#pragma ADDRESS c0lmbr1_addr 0239H /* (BANK1) CAN0 Local Mask B Register 1 */
|
||
|
#pragma ADDRESS c0lmbr2_addr 023aH /* (BANK1) CAN0 Local Mask B Register 2 */
|
||
|
#pragma ADDRESS c0lmbr3_addr 023bH /* (BANK1) CAN0 Local Mask B Register 3 */
|
||
|
#pragma ADDRESS c0lmbr4_addr 023cH /* (BANK1) CAN0 Local Mask B Register 4 */
|
||
|
#pragma ADDRESS c0sbs_addr 0240H /* CAN0 Slot Buffer Select Register */
|
||
|
#pragma ADDRESS c0ctlr1_addr 0241H /* CAN0 Control Register 1 */
|
||
|
#pragma ADDRESS c0slpr_addr 0242H /* CAN0 Sleep Control Register */
|
||
|
#pragma ADDRESS c0afs_addr 0244H /* CAN0 Acceptance Filter Support Register */
|
||
|
|
||
|
|
||
|
/************************************************************************
|
||
|
* CAN 1 SFR Address area *
|
||
|
************************************************************************/
|
||
|
#pragma ADDRESS c1slot 0260H /* CAN1 Message Slot Buffer */
|
||
|
#pragma ADDRESS c1slot0 0260H /* CAN1 Message Slot Buffer 0 */
|
||
|
#pragma ADDRESS c1slot1 0270H /* CAN1 Message Slot Buffer 1 */
|
||
|
#pragma ADDRESS c1ctlr0_addr 0280H /* CAN1 Control Register 0 */
|
||
|
#pragma ADDRESS c1str_addr 0282H /* CAN1 Status Register */
|
||
|
#pragma ADDRESS c1idr_addr 0284H /* CAN1 Extended ID Register */
|
||
|
#pragma ADDRESS c1conr_addr 0286H /* CAN1 Configuration Register */
|
||
|
#pragma ADDRESS c1tsr_addr 0288H /* CAN1 Time Stamp Register */
|
||
|
#pragma ADDRESS c1tec_addr 028aH /* CAN1 Transmit Error Counter */
|
||
|
#pragma ADDRESS c1rec_addr 028bH /* CAN1 Receive Error Counter */
|
||
|
#pragma ADDRESS c1sistr_addr 028cH /* CAN1 Slot Interrupt Status Register */
|
||
|
#pragma ADDRESS c1simkr_addr 0290H /* CAN1 Slot Interrupt Mask Register */
|
||
|
#pragma ADDRESS c1eimkr_addr 0294H /* CAN1 Error Interrupt Mask Register */
|
||
|
#pragma ADDRESS c1eistr_addr 0295H /* CAN1 Error Interrupt Status Register */
|
||
|
#pragma ADDRESS c1efr_addr 0296H /* CAN1 Error Factor Register */
|
||
|
#pragma ADDRESS c1brp_addr 0297H /* CAN1 Baud Rate Prescaler */
|
||
|
#pragma ADDRESS c1mdr_addr 0299H /* CAN1 Mode Register */
|
||
|
#pragma ADDRESS c1ssctlr_addr 02A0H /* (BANK0) CAN1 Single Shot Control Register */
|
||
|
#pragma ADDRESS c1ssstr_addr 02A4H /* (BANK0) CAN1 Single Shot Status Register */
|
||
|
#pragma ADDRESS c1mctl 02B0H /* (BANK0) CAN1 Message Control Register */
|
||
|
#pragma ADDRESS c1mctl0 02B0H /* (BANK0) CAN1 Message Slot0 Control Register */
|
||
|
#pragma ADDRESS c1mctl1 02B1H /* (BANK0) CAN1 Message Slot1 Control Register */
|
||
|
#pragma ADDRESS c1mctl2 02B2H /* (BANK0) CAN1 Message Slot2 Control Register */
|
||
|
#pragma ADDRESS c1mctl3 02B3H /* (BANK0) CAN1 Message Slot3 Control Register */
|
||
|
#pragma ADDRESS c1mctl4 02B4H /* (BANK0) CAN1 Message Slot4 Control Register */
|
||
|
#pragma ADDRESS c1mctl5 02B5H /* (BANK0) CAN1 Message Slot5 Control Register */
|
||
|
#pragma ADDRESS c1mctl6 02B6H /* (BANK0) CAN1 Message Slot6 Control Register */
|
||
|
#pragma ADDRESS c1mctl7 02B7H /* (BANK0) CAN1 Message Slot7 Control Register */
|
||
|
#pragma ADDRESS c1mctl8 02B8H /* (BANK0) CAN1 Message Slot8 Control Register */
|
||
|
#pragma ADDRESS c1mctl9 02B9H /* (BANK0) CAN1 Message Slot9 Control Register */
|
||
|
#pragma ADDRESS c1mctl10 02baH /* (BANK0) CAN1 Message Slot10 Control Register */
|
||
|
#pragma ADDRESS c1mctl11 02bbH /* (BANK0) CAN1 Message Slot11 Control Register */
|
||
|
#pragma ADDRESS c1mctl12 02bcH /* (BANK0) CAN1 Message Slot12 Control Register */
|
||
|
#pragma ADDRESS c1mctl13 02bdH /* (BANK0) CAN1 Message Slot13 Control Register */
|
||
|
#pragma ADDRESS c1mctl14 02beH /* (BANK0) CAN1 Message Slot14 Control Register */
|
||
|
#pragma ADDRESS c1mctl15 02bfH /* (BANK0) CAN1 Message Slot15 Control Register */
|
||
|
#pragma ADDRESS c1gmr 02a8H /* (BANK1) CAN1 Global Mask Register */
|
||
|
#pragma ADDRESS c1gmr0_addr 02a8H /* (BANK1) CAN1 Global Mask Register 0 */
|
||
|
#pragma ADDRESS c1gmr1_addr 02a9H /* (BANK1) CAN1 Global Mask Register 1 */
|
||
|
#pragma ADDRESS c1gmr2_addr 02aaH /* (BANK1) CAN1 Global Mask Register 2 */
|
||
|
#pragma ADDRESS c1gmr3_addr 02abH /* (BANK1) CAN1 Global Mask Register 3 */
|
||
|
#pragma ADDRESS c1gmr4_addr 02acH /* (BANK1) CAN1 Global Mask Register 4 */
|
||
|
#pragma ADDRESS c1lmar 02b0H /* (BANK1) CAN1 Local Mask A Register */
|
||
|
#pragma ADDRESS c1lmar0_addr 02b0H /* (BANK1) CAN1 Local Mask A Register 0 */
|
||
|
#pragma ADDRESS c1lmar1_addr 02b1H /* (BANK1) CAN1 Local Mask A Register 1 */
|
||
|
#pragma ADDRESS c1lmar2_addr 02b2H /* (BANK1) CAN1 Local Mask A Register 2 */
|
||
|
#pragma ADDRESS c1lmar3_addr 02b3H /* (BANK1) CAN1 Local Mask A Register 3 */
|
||
|
#pragma ADDRESS c1lmar4_addr 02b4H /* (BANK1) CAN1 Local Mask A Register 4 */
|
||
|
#pragma ADDRESS c1lmbr 02b8H /* (BANK1) CAN1 Local Mask B Register */
|
||
|
#pragma ADDRESS c1lmbr0_addr 02b8H /* (BANK1) CAN1 Local Mask B Register 0 */
|
||
|
#pragma ADDRESS c1lmbr1_addr 02b9H /* (BANK1) CAN1 Local Mask B Register 1 */
|
||
|
#pragma ADDRESS c1lmbr2_addr 02baH /* (BANK1) CAN1 Local Mask B Register 2 */
|
||
|
#pragma ADDRESS c1lmbr3_addr 02bbH /* (BANK1) CAN1 Local Mask B Register 3 */
|
||
|
#pragma ADDRESS c1lmbr4_addr 02bcH /* (BANK1) CAN1 Local Mask B Register 4 */
|
||
|
#pragma ADDRESS c1sbs_addr 0250H /* CAN1 Slot Buffer Select Register */
|
||
|
#pragma ADDRESS c1ctlr1_addr 0251H /* CAN1 Control Register 1 */
|
||
|
#pragma ADDRESS c1slpr_addr 0252H /* CAN1 Sleep Control Register */
|
||
|
#pragma ADDRESS c1afs_addr 0254H /* CAN1 Acceptance Filter Support Register */
|
||
|
|
||
|
/************************************************************************
|
||
|
* *
|
||
|
************************************************************************/
|
||
|
#pragma ADDRESS x0r_addr 02c0H /* X0 register */
|
||
|
#pragma ADDRESS y0r_addr 02c0H /* Y0 register */
|
||
|
#pragma ADDRESS x1r_addr 02c2H /* X1 register */
|
||
|
#pragma ADDRESS y1r_addr 02c2H /* Y1 register */
|
||
|
#pragma ADDRESS x2r_addr 02c4H /* X2 register */
|
||
|
#pragma ADDRESS y2r_addr 02c4H /* Y2 register */
|
||
|
#pragma ADDRESS x3r_addr 02c6H /* X3 register */
|
||
|
#pragma ADDRESS y3r_addr 02c6H /* Y3 register */
|
||
|
#pragma ADDRESS x4r_addr 02c8H /* X4 register */
|
||
|
#pragma ADDRESS y4r_addr 02c8H /* Y4 register */
|
||
|
#pragma ADDRESS x5r_addr 02caH /* X5 register */
|
||
|
#pragma ADDRESS y5r_addr 02caH /* Y5 register */
|
||
|
#pragma ADDRESS x6r_addr 02ccH /* X6 register */
|
||
|
#pragma ADDRESS y6r_addr 02ccH /* Y6 register */
|
||
|
#pragma ADDRESS x7r_addr 02ceH /* X7 register */
|
||
|
#pragma ADDRESS y7r_addr 02ceH /* Y7 register */
|
||
|
#pragma ADDRESS x8r_addr 02d0H /* X8 register */
|
||
|
#pragma ADDRESS y8r_addr 02d0H /* Y8 register */
|
||
|
#pragma ADDRESS x9r_addr 02d2H /* X9 register */
|
||
|
#pragma ADDRESS y9r_addr 02d2H /* Y9 register */
|
||
|
#pragma ADDRESS x10r_addr 02d4H /* X10 register */
|
||
|
#pragma ADDRESS y10r_addr 02d4H /* Y10 register */
|
||
|
#pragma ADDRESS x11r_addr 02d6H /* X11 register */
|
||
|
#pragma ADDRESS y11r_addr 02d6H /* Y11 register */
|
||
|
#pragma ADDRESS x12r_addr 02d8H /* X12 register */
|
||
|
#pragma ADDRESS y12r_addr 02d8H /* Y12 register */
|
||
|
#pragma ADDRESS x13r_addr 02daH /* X13 register */
|
||
|
#pragma ADDRESS y13r_addr 02daH /* Y13 register */
|
||
|
#pragma ADDRESS x14r_addr 02dcH /* X14 register */
|
||
|
#pragma ADDRESS y14r_addr 02dcH /* Y14 register */
|
||
|
#pragma ADDRESS x15r_addr 02deH /* X15 register */
|
||
|
#pragma ADDRESS y15r_addr 02deH /* Y15 register */
|
||
|
#pragma ADDRESS xyc_addr 02e0H /* X-Y control register */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS u1smr4_addr 02e4H /* UART1 special mode register 4 */
|
||
|
#pragma ADDRESS u1smr3_addr 02e5H /* UART1 special mode register 3 */
|
||
|
#pragma ADDRESS u1smr2_addr 02e6H /* UART1 special mode register 2 */
|
||
|
#pragma ADDRESS u1smr_addr 02e7H /* UART1 special mode register */
|
||
|
#pragma ADDRESS u1mr_addr 02e8H /* UART1 transmit/receive mode register */
|
||
|
#pragma ADDRESS u1brg_addr 02e9H /* UART1 bit rate generator */
|
||
|
#pragma ADDRESS u1tb_addr 02eaH /* UART1 transmit buffer register */
|
||
|
#pragma ADDRESS u1c0_addr 02ecH /* UART1 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u1c1_addr 02edH /* UART1 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u1rb_addr 02eeH /* UART1 receive buffer register */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS u4smr4_addr 02f4H /* UART4 special mode register 4 */
|
||
|
#pragma ADDRESS u4smr3_addr 02f5H /* UART4 special mode register 3 */
|
||
|
#pragma ADDRESS u4smr2_addr 02f6H /* UART4 special mode register 2 */
|
||
|
#pragma ADDRESS u4smr_addr 02f7H /* UART4 special mode register */
|
||
|
#pragma ADDRESS u4mr_addr 02f8H /* UART4 transmit/receive mode register */
|
||
|
#pragma ADDRESS u4brg_addr 02f9H /* UART4 bit rate generator */
|
||
|
#pragma ADDRESS u4tb_addr 02faH /* UART4 transmit buffer register */
|
||
|
#pragma ADDRESS u4c0_addr 02fcH /* UART4 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u4c1_addr 02fdH /* UART4 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u4rb_addr 02feH /* UART4 receive buffer register */
|
||
|
|
||
|
#pragma ADDRESS tbsr_addr 0300H /* Timer B3,4,5 count start flag */
|
||
|
|
||
|
#pragma ADDRESS ta11_addr 0302H /* Timer A1-1 register */
|
||
|
#pragma ADDRESS ta21_addr 0304H /* Timer A2-1 register */
|
||
|
#pragma ADDRESS ta41_addr 0306H /* Timer A4-1 register */
|
||
|
#pragma ADDRESS invc0_addr 0308H /* Three-phase PWM control register 0 */
|
||
|
#pragma ADDRESS invc1_addr 0309H /* Three-phase PWM control register 1 */
|
||
|
#pragma ADDRESS idb0_addr 030aH /* Three-phase output buffer register 0 */
|
||
|
#pragma ADDRESS idb1_addr 030bH /* Three-phase output buffer register 1 */
|
||
|
#pragma ADDRESS dtt_addr 030cH /* Dead time timer */
|
||
|
#pragma ADDRESS ictb2_addr 030dH /* Timer B2 interrupt occurences frequency set counter */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS tb3_addr 0310H /* Timer B3 register */
|
||
|
#pragma ADDRESS tb4_addr 0312H /* Timer B4 register */
|
||
|
#pragma ADDRESS tb5_addr 0314H /* Timer B5 register */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS tb3mr_addr 031bH /* Timer B3 mode register */
|
||
|
#pragma ADDRESS tb4mr_addr 031cH /* Timer B4 mode register */
|
||
|
#pragma ADDRESS tb5mr_addr 031dH /* Timer B5 mode register */
|
||
|
#pragma ADDRESS ifsra_addr 031eH /* External interrupt request cause select register 1 */
|
||
|
#pragma ADDRESS ifsr_addr 031fH /* External interrupt request cause select register */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS u3smr4_addr 0324H /* UART3 special mode register 4 */
|
||
|
#pragma ADDRESS u3smr3_addr 0325H /* UART3 special mode register 3 */
|
||
|
#pragma ADDRESS u3smr2_addr 0326H /* UART3 special mode register 2 */
|
||
|
#pragma ADDRESS u3smr_addr 0327H /* UART3 special mode register */
|
||
|
#pragma ADDRESS u3mr_addr 0328H /* UART3 transmit/receive mode register */
|
||
|
#pragma ADDRESS u3brg_addr 0329H /* UART3 bit rate generator */
|
||
|
#pragma ADDRESS u3tb_addr 032aH /* UART3 transmit buffer register */
|
||
|
#pragma ADDRESS u3c0_addr 032cH /* UART3 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u3c1_addr 032dH /* UART3 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u3rb_addr 032eH /* UART3 receive buffer register */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS u2smr4_addr 0334H /* UART2 special mode register 4 */
|
||
|
#pragma ADDRESS u2smr3_addr 0335H /* UART2 special mode register 3 */
|
||
|
#pragma ADDRESS u2smr2_addr 0336H /* UART2 special mode register 2 */
|
||
|
#pragma ADDRESS u2smr_addr 0337H /* UART2 special mode register */
|
||
|
#pragma ADDRESS u2mr_addr 0338H /* UART2 transmit/receive mode register */
|
||
|
#pragma ADDRESS u2brg_addr 0339H /* UART2 bit rate generator */
|
||
|
#pragma ADDRESS u2tb_addr 033aH /* UART2 transmit buffer register */
|
||
|
#pragma ADDRESS u2c0_addr 033cH /* UART2 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u2c1_addr 033dH /* UART2 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u2rb_addr 033eH /* UART2 receive buffer register */
|
||
|
#pragma ADDRESS tabsr_addr 0340H /* Count start flag */
|
||
|
#pragma ADDRESS cpsrf_addr 0341H /* Clock prescaler reset flag */
|
||
|
#pragma ADDRESS onsf_addr 0342H /* One-shot start flag */
|
||
|
#pragma ADDRESS trgsr_addr 0343H /* Trigger select register */
|
||
|
#pragma ADDRESS udf_addr 0344H /* Up/down flag */
|
||
|
|
||
|
#pragma ADDRESS ta0_addr 0346H /* Timer A0 register */
|
||
|
#pragma ADDRESS ta1_addr 0348H /* Timer A1 register */
|
||
|
#pragma ADDRESS ta2_addr 034aH /* Timer A2 register */
|
||
|
#pragma ADDRESS ta3_addr 034cH /* Timer A3 register */
|
||
|
#pragma ADDRESS ta4_addr 034eH /* Timer A4 register */
|
||
|
#pragma ADDRESS tb0_addr 0350H /* Timer B0 register */
|
||
|
#pragma ADDRESS tb1_addr 0352H /* Timer B1 register */
|
||
|
#pragma ADDRESS tb2_addr 0354H /* Timer B2 register */
|
||
|
#pragma ADDRESS ta0mr_addr 0356H /* Timer A0 mode register */
|
||
|
#pragma ADDRESS ta1mr_addr 0357H /* Timer A1 mode register */
|
||
|
#pragma ADDRESS ta2mr_addr 0358H /* Timer A2 mode register */
|
||
|
#pragma ADDRESS ta3mr_addr 0359H /* Timer A3 mode register */
|
||
|
#pragma ADDRESS ta4mr_addr 035aH /* Timer A4 mode register */
|
||
|
#pragma ADDRESS tb0mr_addr 035bH /* Timer B0 mode register */
|
||
|
#pragma ADDRESS tb1mr_addr 035cH /* Timer B1 mode register */
|
||
|
#pragma ADDRESS tb2mr_addr 035dH /* Timer B2 mode register */
|
||
|
#pragma ADDRESS tb2sc_addr 035eH /* Timer B2 special mode register */
|
||
|
#pragma ADDRESS tcspr_addr 035fH /* Count source prescaler register */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS u0smr4_addr 0364H /* UART0 special mode register 4 */
|
||
|
#pragma ADDRESS u0smr3_addr 0365H /* UART0 special mode register 3 */
|
||
|
#pragma ADDRESS u0smr2_addr 0366H /* UART0 special mode register 2 */
|
||
|
#pragma ADDRESS u0smr_addr 0367H /* UART0 special mode register */
|
||
|
#pragma ADDRESS u0mr_addr 0368H /* UART0 transmit/receive mode register */
|
||
|
#pragma ADDRESS u0brg_addr 0369H /* UART0 bit rate generator */
|
||
|
#pragma ADDRESS u0tb_addr 036aH /* UART0 transmit buffer register */
|
||
|
#pragma ADDRESS u0c0_addr 036cH /* UART0 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u0c1_addr 036dH /* UART0 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u0rb_addr 036eH /* UART0 receive buffer register */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS ircon_addr 0372H
|
||
|
|
||
|
|
||
|
#pragma ADDRESS dm0sl_addr 0378H /* DMA0 cause select register */
|
||
|
#pragma ADDRESS dm1sl_addr 0379H /* DMA1 cause select register */
|
||
|
#pragma ADDRESS dm2sl_addr 037aH /* DMA1 cause select register */
|
||
|
#pragma ADDRESS dm3sl_addr 037bH /* DMA1 cause select register */
|
||
|
#pragma ADDRESS crcd_addr 037cH /* CRC data register */
|
||
|
#pragma ADDRESS crcin_addr 037eH /* CRC input register */
|
||
|
|
||
|
#pragma ADDRESS ad00_addr 0380H /* A/D0 register 0 */
|
||
|
#pragma ADDRESS ad01_addr 0382H /* A/D0 register 1 */
|
||
|
#pragma ADDRESS ad02_addr 0384H /* A/D0 register 2 */
|
||
|
#pragma ADDRESS ad03_addr 0386H /* A/D0 register 3 */
|
||
|
#pragma ADDRESS ad04_addr 0388H /* A/D0 register 4 */
|
||
|
#pragma ADDRESS ad05_addr 038aH /* A/D0 register 5 */
|
||
|
#pragma ADDRESS ad06_addr 038cH /* A/D0 register 6 */
|
||
|
#pragma ADDRESS ad07_addr 038eH /* A/D0 register 7 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS ad0con4_addr 0392H /* A/D0 control register 4 */
|
||
|
|
||
|
#pragma ADDRESS ad0con2_addr 0394H /* A/D0 control register 2 */
|
||
|
#pragma ADDRESS ad0con3_addr 0395H /* A/D0 control register 3 */
|
||
|
#pragma ADDRESS ad0con0_addr 0396H /* A/D0 control register 0 */
|
||
|
#pragma ADDRESS ad0con1_addr 0397H /* A/D0 control register 1 */
|
||
|
#pragma ADDRESS da0_addr 0398H /* D/A register 0 */
|
||
|
|
||
|
#pragma ADDRESS da1_addr 039aH /* D/A register 1 */
|
||
|
|
||
|
#pragma ADDRESS dacon_addr 039cH /* D/A control register */
|
||
|
#pragma ADDRESS dacon1_addr 039dH /* D/A control register 1 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS ps8_addr 03a0H /* Function select register A8 */
|
||
|
#pragma ADDRESS ps9_addr 03a1H /* Function select register A9 */
|
||
|
|
||
|
#pragma ADDRESS psl9_addr 03a3H /* Function select register B9 */
|
||
|
#pragma ADDRESS pse2_addr 03a4H /* Function select register E2 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS psd1_addr 03a7H /* Function select register D1 */
|
||
|
#pragma ADDRESS psd2_addr 03a8H /* Function select register D2 */
|
||
|
|
||
|
#pragma ADDRESS psc6_addr 03aaH /* Function select register C6 */
|
||
|
#pragma ADDRESS pse1_addr 03abH /* Function select register E1 */
|
||
|
#pragma ADDRESS psc2_addr 03acH /* Function select register C2 */
|
||
|
#pragma ADDRESS psc3_addr 03adH /* Function select register C3 */
|
||
|
|
||
|
#pragma ADDRESS psc_addr 03afH /* Function select register C */
|
||
|
#pragma ADDRESS ps0_addr 03b0H /* Function select register A0 */
|
||
|
#pragma ADDRESS ps1_addr 03b1H /* Function select register A1 */
|
||
|
#pragma ADDRESS psl0_addr 03b2H /* Function select register B0 */
|
||
|
#pragma ADDRESS psl1_addr 03b3H /* Function select register B1 */
|
||
|
#pragma ADDRESS ps2_addr 03b4H /* Function select register A2 */
|
||
|
#pragma ADDRESS ps3_addr 03b5H /* Function select register A3 */
|
||
|
#pragma ADDRESS psl2_addr 03b6H /* Function select register B2 */
|
||
|
#pragma ADDRESS psl3_addr 03b7H /* Function select register B3 */
|
||
|
#pragma ADDRESS ps4_addr 03b8H /* Function select register A4 */
|
||
|
#pragma ADDRESS ps5_addr 03b9H /* Function select register A5 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS ps6_addr 03bcH /* Function select register A6 */
|
||
|
#pragma ADDRESS ps7_addr 03bdH /* Function select register A7 */
|
||
|
#pragma ADDRESS psl6_addr 03beH /* Function select register B6 */
|
||
|
|
||
|
#pragma ADDRESS p6_addr 03c0H /* Port P6 register */
|
||
|
#pragma ADDRESS p7_addr 03c1H /* Port P7 register */
|
||
|
#pragma ADDRESS pd6_addr 03c2H /* Port P6 direction register */
|
||
|
#pragma ADDRESS pd7_addr 03c3H /* Port P7 direction register */
|
||
|
#pragma ADDRESS p8_addr 03c4H /* Port P8 register */
|
||
|
#pragma ADDRESS p9_addr 03c5H /* Port P9 register */
|
||
|
#pragma ADDRESS pd8_addr 03c6H /* Port P8 direction register */
|
||
|
#pragma ADDRESS pd9_addr 03c7H /* Port P9 direction register */
|
||
|
#pragma ADDRESS p10_addr 03c8H /* Port P10 register */
|
||
|
#pragma ADDRESS p11_addr 03c9H /* Port P11 register */
|
||
|
#pragma ADDRESS pd10_addr 03caH /* Port P10 direction register */
|
||
|
#pragma ADDRESS pd11_addr 03cbH /* Port P11 direction register */
|
||
|
#pragma ADDRESS p12_addr 03ccH /* Port P12 register */
|
||
|
#pragma ADDRESS p13_addr 03cdH /* Port P13 register */
|
||
|
#pragma ADDRESS pd12_addr 03ceH /* Port P12 direction register */
|
||
|
#pragma ADDRESS pd13_addr 03cfH /* Port P13 direction register */
|
||
|
#pragma ADDRESS p14_addr 03d0H /* Port P14 register */
|
||
|
#pragma ADDRESS p15_addr 03d1H /* Port P15 register */
|
||
|
#pragma ADDRESS pd14_addr 03d2H /* Port P14 direction register */
|
||
|
#pragma ADDRESS pd15_addr 03d3H /* Port P15 direction register */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS pur2_addr 03daH /* Pull-up control register 2 */
|
||
|
#pragma ADDRESS pur3_addr 03dbH /* Pull-up control register 3 */
|
||
|
#pragma ADDRESS pur4_addr 03dcH /* Pull-up control register 4 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS p0_addr 03e0H /* Port P0 register */
|
||
|
#pragma ADDRESS p1_addr 03e1H /* Port P1 register */
|
||
|
#pragma ADDRESS pd0_addr 03e2H /* Port P0 direction register */
|
||
|
#pragma ADDRESS pd1_addr 03e3H /* Port P1 direction register */
|
||
|
#pragma ADDRESS p2_addr 03e4H /* Port P2 register */
|
||
|
#pragma ADDRESS p3_addr 03e5H /* Port P3 register */
|
||
|
#pragma ADDRESS pd2_addr 03e6H /* Port P2 direction register */
|
||
|
#pragma ADDRESS pd3_addr 03e7H /* Port P3 direction register */
|
||
|
#pragma ADDRESS p4_addr 03e8H /* Port P4 register */
|
||
|
#pragma ADDRESS p5_addr 03e9H /* Port P5 register */
|
||
|
#pragma ADDRESS pd4_addr 03eaH /* Port P4 direction register */
|
||
|
#pragma ADDRESS pd5_addr 03ebH /* Port P5 direction register */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS pur0_addr 03f0H /* Pull-up control register 0 */
|
||
|
#pragma ADDRESS pur1_addr 03f1H /* Pull-up control register 1 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS pcr_addr 03ffH /* Port control register */
|
||
|
|
||
|
|
||
|
/*******************************************************
|
||
|
* declare SFR char *
|
||
|
********************************************************/
|
||
|
unsigned char da0_addr; /* D/A register 0 */
|
||
|
#define da0 da0_addr
|
||
|
|
||
|
unsigned char da1_addr; /* D/A register 1 */
|
||
|
#define da1 da1_addr
|
||
|
|
||
|
/********************************************************
|
||
|
* declare SFR short *
|
||
|
********************************************************/
|
||
|
/*---------------------------------------------------------------------
|
||
|
Timer registers ; Read and write to this register in 16-bit units.
|
||
|
-----------------------------------------------------------------------*/
|
||
|
unsigned short ta11_addr; /* Timer A1-1 register */
|
||
|
#define ta11 ta11_addr
|
||
|
|
||
|
unsigned short ta21_addr; /* Timer A2-1 register */
|
||
|
#define ta21 ta21_addr
|
||
|
|
||
|
unsigned short ta41_addr; /* Timer A4-1 register */
|
||
|
#define ta41 ta41_addr
|
||
|
|
||
|
unsigned short tb3_addr; /* Timer B3 register */
|
||
|
#define tb3 tb3_addr
|
||
|
|
||
|
unsigned short tb4_addr; /* Timer B4 register */
|
||
|
#define tb4 tb4_addr
|
||
|
|
||
|
unsigned short tb5_addr; /* Timer B5 register */
|
||
|
#define tb5 tb5_addr
|
||
|
|
||
|
unsigned short ta0_addr; /* Timer A0 register */
|
||
|
#define ta0 ta0_addr
|
||
|
|
||
|
unsigned short ta1_addr; /* Timer A1 register */
|
||
|
#define ta1 ta1_addr
|
||
|
|
||
|
unsigned short ta2_addr; /* Timer A2 register */
|
||
|
#define ta2 ta2_addr
|
||
|
|
||
|
unsigned short ta3_addr; /* Timer A3 register */
|
||
|
#define ta3 ta3_addr
|
||
|
|
||
|
unsigned short ta4_addr; /* Timer A4 register */
|
||
|
#define ta4 ta4_addr
|
||
|
|
||
|
unsigned short tb0_addr; /* Timer B0 register */
|
||
|
#define tb0 tb0_addr
|
||
|
|
||
|
unsigned short tb1_addr; /* Timer B1 register */
|
||
|
#define tb1 tb1_addr
|
||
|
|
||
|
unsigned short tb2_addr; /* Timer B2 register */
|
||
|
#define tb2 tb2_addr
|
||
|
|
||
|
/*---------------------------------------------------------------------
|
||
|
IIO registers ; Read and write to this register in 16-bit units.
|
||
|
-----------------------------------------------------------------------*/
|
||
|
|
||
|
/********************************************************
|
||
|
* group 0 and 1 and 2 *
|
||
|
********************************************************/
|
||
|
#define g1bt g1bt_addr.word /* Base Timer Register 1 */
|
||
|
#define g1btl g1bt_addr.byte.low
|
||
|
#define g1bth g1bt_addr.byte.high
|
||
|
|
||
|
#define g1tm0 g1tm0_addr.word /* Time Measurement Register 10 */
|
||
|
#define g1tm0l g1tm0_addr.byte.low
|
||
|
#define g1tm0h g1tm0_addr.byte.high
|
||
|
|
||
|
#define g1tm1 g1tm1_addr.word /* Time Measurement Register 11 */
|
||
|
#define g1tm1l g1tm1_addr.byte.low
|
||
|
#define g1tm1h g1tm1_addr.byte.high
|
||
|
|
||
|
#define g1tm2 g1tm2_addr.word /* Time Measurement Register 12 */
|
||
|
#define g1tm2l g1tm2_addr.byte.low
|
||
|
#define g1tm2h g1tm2_addr.byte.high
|
||
|
|
||
|
#define g1tm3 g1tm3_addr.word /* Time Measurement Register 13 */
|
||
|
#define g1tm3l g1tm3_addr.byte.low
|
||
|
#define g1tm3h g1tm3_addr.byte.high
|
||
|
|
||
|
#define g1tm4 g1tm4_addr.word /* Time Measurement Register 14 */
|
||
|
#define g1tm4l g1tm4_addr.byte.low
|
||
|
#define g1tm4h g1tm4_addr.byte.high
|
||
|
|
||
|
#define g1tm5 g1tm5_addr.word /* Time Measurement Register 15 */
|
||
|
#define g1tm5l g1tm5_addr.byte.low
|
||
|
#define g1tm5h g1tm5_addr.byte.high
|
||
|
|
||
|
#define g1tm6 g1tm6_addr.word /* Time Measurement Register 16 */
|
||
|
#define g1tm6l g1tm6_addr.byte.low
|
||
|
#define g1tm6h g1tm6_addr.byte.high
|
||
|
|
||
|
#define g1tm7 g1tm7_addr.word /* Time Measurement Register 17 */
|
||
|
#define g1tm7l g1tm7_addr.byte.low
|
||
|
#define g1tm7h g1tm7_addr.byte.high
|
||
|
|
||
|
#define g1po0 g1po0_addr.word /* Waveform Generate Register 10 */
|
||
|
#define g1po0l g1po0_addr.byte.low
|
||
|
#define g1po0h g1po0_addr.byte.high
|
||
|
|
||
|
#define g1po1 g1po1_addr.word /* Waveform Generate Register 11 */
|
||
|
#define g1po1l g1po1_addr.byte.low
|
||
|
#define g1po1h g1po1_addr.byte.high
|
||
|
|
||
|
#define g1po2 g1po2_addr.word /* Waveform Generate Register 12 */
|
||
|
#define g1po2l g1po2_addr.byte.low
|
||
|
#define g1po2h g1po2_addr.byte.high
|
||
|
|
||
|
#define g1po3 g1po3_addr.word /* Waveform Generate Register 13 */
|
||
|
#define g1po3l g1po3_addr.byte.low
|
||
|
#define g1po3h g1po3_addr.byte.high
|
||
|
|
||
|
#define g1po4 g1po4_addr.word /* Waveform Generate Register 14 */
|
||
|
#define g1po4l g1po4_addr.byte.low
|
||
|
#define g1po4h g1po4_addr.byte.high
|
||
|
|
||
|
#define g1po5 g1po5_addr.word /* Waveform Generate Register 15 */
|
||
|
#define g1po5l g1po5_addr.byte.low
|
||
|
#define g1po5h g1po5_addr.byte.high
|
||
|
|
||
|
#define g1po6 g1po6_addr.word /* Waveform Generate Register 16 */
|
||
|
#define g1po6l g1po6_addr.byte.low
|
||
|
#define g1po6h g1po6_addr.byte.high
|
||
|
|
||
|
#define g1po7 g1po7_addr.word /* Waveform Generate Register 17 */
|
||
|
#define g1po7l g1po7_addr.byte.low
|
||
|
#define g1po7h g1po7_addr.byte.high
|
||
|
|
||
|
#define g2bt g2bt_addr.word /* Base Timer Register 2 */
|
||
|
#define g2btl g2bt_addr.byte.low
|
||
|
#define g2bth g2bt_addr.byte.high
|
||
|
|
||
|
#define g2po0 g2po0_addr.word /* Waveform Generate Register 20 */
|
||
|
#define g2po0l g2po0_addr.byte.low
|
||
|
#define g2po0h g2po0_addr.byte.high
|
||
|
|
||
|
#define g2po1 g2po1_addr.word /* Waveform Generate Register 21 */
|
||
|
#define g2po1l g2po1_addr.byte.low
|
||
|
#define g2po1h g2po1_addr.byte.high
|
||
|
|
||
|
#define g2po2 g2po2_addr.word /* Waveform Generate Register 22 */
|
||
|
#define g2po2l g2po2_addr.byte.low
|
||
|
#define g2po2h g2po2_addr.byte.high
|
||
|
|
||
|
#define g2po3 g2po3_addr.word /* Waveform Generate Register 23 */
|
||
|
#define g2po3l g2po3_addr.byte.low
|
||
|
#define g2po3h g2po3_addr.byte.high
|
||
|
|
||
|
#define g2po4 g2po4_addr.word /* Waveform Generate Register 24 */
|
||
|
#define g2po4l g2po4_addr.byte.low
|
||
|
#define g2po4h g2po4_addr.byte.high
|
||
|
|
||
|
#define g2po5 g2po5_addr.word /* Waveform Generate Register 25 */
|
||
|
#define g2po5l g2po5_addr.byte.low
|
||
|
#define g2po5h g2po5_addr.byte.high
|
||
|
|
||
|
#define g2po6 g2po6_addr.word /* Waveform Generate Register 26 */
|
||
|
#define g2po6l g2po6_addr.byte.low
|
||
|
#define g2po6h g2po6_addr.byte.high
|
||
|
|
||
|
#define g2po7 g2po7_addr.word /* Waveform Generate Register 27 */
|
||
|
#define g2po7l g2po7_addr.byte.low
|
||
|
#define g2po7h g2po7_addr.byte.high
|
||
|
|
||
|
#define g0tcrc g0tcrc_addr.word /* Transmit CRC Code Register 0 */
|
||
|
#define g0tcrcl g0tcrc_addr.byte.low
|
||
|
#define g0tcrch g0tcrc_addr.byte.high
|
||
|
|
||
|
#define g1tcrc g1tcrc_addr.word /* Transmit CRC Code Register 1 */
|
||
|
#define g1tcrcl g1tcrc_addr.byte.low
|
||
|
#define g1tcrch g1tcrc_addr.byte.high
|
||
|
|
||
|
#define g0rcrc g0rcrc_addr.word /* Receive CRC Code Register 0 */
|
||
|
#define g0rcrcl g0rcrc_addr.byte.low
|
||
|
#define g0rcrch g0rcrc_addr.byte.high
|
||
|
|
||
|
#define g1rcrc g1rcrc_addr.word /* Receive CRC Code Register 1 */
|
||
|
#define g1rcrcl g1rcrc_addr.byte.low
|
||
|
#define g1rcrch g1rcrc_addr.byte.high
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
SI/O receive buffer register
|
||
|
------------------------------------------------------*/
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
SI/O Receive Buffer Register 0
|
||
|
------------------------------------------------------*/
|
||
|
#define g0rb g0rb_addr.word
|
||
|
#define g0rbl g0rb_addr.byte.low
|
||
|
#define g0rbh g0rb_addr.byte.high
|
||
|
#define oer_g0rb g0rb_addr.bit.b12 /* Overrun error flag */
|
||
|
#define fer_g0rb g0rb_addr.bit.b13 /* Framing error flag */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
SI/O Receive Buffer Register 1
|
||
|
------------------------------------------------------*/
|
||
|
#define g1rb g1rb_addr.word
|
||
|
#define g1rbl g1rb_addr.byte.low
|
||
|
#define g1rbh g1rb_addr.byte.high
|
||
|
#define oer_g1rb g1rb_addr.bit.b12 /* Overrun error flag */
|
||
|
#define fer_g1rb g1rb_addr.bit.b13 /* Framing error flag */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
SI/O Receive Buffer Register 2
|
||
|
------------------------------------------------------*/
|
||
|
#define g2rb g2rb_addr.word
|
||
|
#define g2rbl g2rb_addr.byte.low
|
||
|
#define g2rbh g2rb_addr.byte.high
|
||
|
#define oer_g2rb g2rb_addr.bit.b12 /* Overrun error flag */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
SI/O Transmit Buffer Register 2
|
||
|
------------------------------------------------------*/
|
||
|
#define g2tb g2tb_addr.word
|
||
|
#define g2tbl g2tb_addr.byte.low
|
||
|
#define g2tbh g2tb_addr.byte.high
|
||
|
#define a_g2tb g2tb_addr.bit.b13
|
||
|
#define pc_g2tb g2tb_addr.bit.b14
|
||
|
#define p_g2tb g2tb_addr.bit.b15
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
|
||
|
------------------------------------------------------*/
|
||
|
#define iear iear_addr.word
|
||
|
#define iearl iear_addr.byte.low
|
||
|
#define iearh iear_addr.byte.high
|
||
|
|
||
|
/********************************************************
|
||
|
* declare SFR bit *
|
||
|
********************************************************/
|
||
|
struct bit_def {
|
||
|
char b0:1;
|
||
|
char b1:1;
|
||
|
char b2:1;
|
||
|
char b3:1;
|
||
|
char b4:1;
|
||
|
char b5:1;
|
||
|
char b6:1;
|
||
|
char b7:1;
|
||
|
};
|
||
|
union byte_def{
|
||
|
struct bit_def bit;
|
||
|
char byte;
|
||
|
};
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
External Space Wait Control Register 0
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def ewcr0_addr;
|
||
|
#define ewcr0 ewcr0_addr.byte
|
||
|
|
||
|
#define ewcr000 ewcr0_addr.bit.b0 /* (b4-b0) Bus cycle select bit */
|
||
|
#define ewcr001 ewcr0_addr.bit.b1
|
||
|
#define ewcr002 ewcr0_addr.bit.b2
|
||
|
#define ewcr003 ewcr0_addr.bit.b3
|
||
|
#define ewcr004 ewcr0_addr.bit.b4
|
||
|
/* (b5) Nothing is assigned */
|
||
|
#define ewcr006 ewcr0_addr.bit.b6 /* Recovery cycle addition select bit */
|
||
|
/* (b7) Nothing is assigned */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
External Space Wait Control Register 1
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def ewcr1_addr;
|
||
|
#define ewcr1 ewcr1_addr.byte
|
||
|
|
||
|
#define ewcr100 ewcr1_addr.bit.b0 /* (b4-b0) Bus cycle select bit */
|
||
|
#define ewcr101 ewcr1_addr.bit.b1
|
||
|
#define ewcr102 ewcr1_addr.bit.b2
|
||
|
#define ewcr103 ewcr1_addr.bit.b3
|
||
|
#define ewcr104 ewcr1_addr.bit.b4
|
||
|
/* (b5) Nothing is assigned */
|
||
|
#define ewcr106 ewcr1_addr.bit.b6 /* Recovery cycle addition select bit */
|
||
|
/* (b7) Nothing is assigned */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
External Space Wait Control Register 2
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def ewcr2_addr;
|
||
|
#define ewcr2 ewcr2_addr.byte
|
||
|
|
||
|
#define ewcr200 ewcr2_addr.bit.b0 /* (b4-b0) Bus cycle select bit */
|
||
|
#define ewcr201 ewcr2_addr.bit.b1
|
||
|
#define ewcr202 ewcr2_addr.bit.b2
|
||
|
#define ewcr203 ewcr2_addr.bit.b3
|
||
|
#define ewcr204 ewcr2_addr.bit.b4
|
||
|
/* (b5) Nothing is assigned */
|
||
|
#define ewcr206 ewcr2_addr.bit.b6 /* Recovery cycle addition select bit */
|
||
|
/* (b7) Nothing is assigned */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
External Space Wait Control Register 3
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def ewcr3_addr;
|
||
|
#define ewcr3 ewcr3_addr.byte
|
||
|
|
||
|
#define ewcr300 ewcr3_addr.bit.b0 /* (b4-b0) Bus cycle select bit */
|
||
|
#define ewcr301 ewcr3_addr.bit.b1
|
||
|
#define ewcr302 ewcr3_addr.bit.b2
|
||
|
#define ewcr303 ewcr3_addr.bit.b3
|
||
|
#define ewcr304 ewcr3_addr.bit.b4
|
||
|
/* (b5) Nothing is assigned */
|
||
|
#define ewcr306 ewcr3_addr.bit.b6 /* Recovery cycle addition select bit */
|
||
|
/* (b7) Nothing is assigned */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Flash Memory control register 1
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def fmr1_addr;
|
||
|
#define fmr1 fmr1_addr.byte
|
||
|
/* (b0) Reserved bit */
|
||
|
#define fmr11 fmr1_addr.bit.b1 /* EW1 mode select bit */
|
||
|
/* (b3-b2) Reserved bit */
|
||
|
/* (b5-b4) Reserved bit */
|
||
|
#define fmr16 fmr1_addr.bit.b6 /* Lock bit status flag */
|
||
|
/* (b7) Reserved bit (Set to 0) */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Flash Memory control register 0
|
||
|
------------------------------------------------------*/
|
||
|
#define fmr fmr_addr.word
|
||
|
|
||
|
union byte_def fmr0_addr;
|
||
|
#define fmr0 fmr0_addr.byte
|
||
|
|
||
|
#define fmr00 fmr0_addr.bit.b0 /* RY/BY status flag */
|
||
|
#define fmr01 fmr0_addr.bit.b1 /* CPU rewrite mode select bit */
|
||
|
#define fmr02 fmr0_addr.bit.b2 /* Lock bit disable select bit */
|
||
|
#define fmstp fmr0_addr.bit.b3 /* Flash memory stop bit */
|
||
|
/* (b4) Reserved bit (Set to 0) */
|
||
|
#define fmr05 fmr0_addr.bit.b5 /* User ROM area select bit (Available in boot mode only) */
|
||
|
#define fmr06 fmr0_addr.bit.b6 /* Program status flag */
|
||
|
#define fmr07 fmr0_addr.bit.b7 /* Erase status flag */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Processor mode register 0
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def pm0_addr;
|
||
|
#define pm0 pm0_addr.byte
|
||
|
|
||
|
#define pm00 pm0_addr.bit.b0 /* Processor mode bit */
|
||
|
#define pm01 pm0_addr.bit.b1 /* Processor mode bit */
|
||
|
#define pm02 pm0_addr.bit.b2 /* R/W mode select bit */
|
||
|
#define pm03 pm0_addr.bit.b3 /* Software reset bit */
|
||
|
#define pm04 pm0_addr.bit.b4 /* Multiplexed bus space select bit */
|
||
|
#define pm05 pm0_addr.bit.b5 /* Multiplexed bus space select bit */
|
||
|
/* (b6) Reserved bit (Set to 0) */
|
||
|
#define pm07 pm0_addr.bit.b7 /* BCLK output function select bit */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Processor mode register 1
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def pm1_addr;
|
||
|
#define pm1 pm1_addr.byte
|
||
|
|
||
|
#define pm10 pm1_addr.bit.b0 /* External memory area mode bit */
|
||
|
#define pm11 pm1_addr.bit.b1 /* External memory area mode bit */
|
||
|
#define pm12 pm1_addr.bit.b2 /* Internal memory wait bit */
|
||
|
#define pm13 pm1_addr.bit.b3 /* SFR wait bit */
|
||
|
#define pm14 pm1_addr.bit.b4 /* ALE pin select bit */
|
||
|
#define pm15 pm1_addr.bit.b5 /* ALE pin select bit */
|
||
|
/* (b7-b6) Reserved bit (Set to 0) */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Processor mode register 2
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def pm2_addr;
|
||
|
#define pm2 pm2_addr.byte
|
||
|
/* (b0) Reserved bit (Set to 0) */
|
||
|
#define pm21 pm2_addr.bit.b1 /* System clock protect bit */
|
||
|
#define pm22 pm2_addr.bit.b2 /* WDT count source protect bit */
|
||
|
/* (b5-b3) Reserved bit (Set to 0) */
|
||
|
#define pm26 pm2_addr.bit.b6 /* (b7-b6) f2n count source select bit */
|
||
|
#define pm27 pm2_addr.bit.b7
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
System clock control register 0
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def cm0_addr;
|
||
|
#define cm0 cm0_addr.byte
|
||
|
|
||
|
#define cm00 cm0_addr.bit.b0 /* Clock output function select bit */
|
||
|
#define cm01 cm0_addr.bit.b1 /* Clock output function select bit */
|
||
|
#define cm02 cm0_addr.bit.b2 /* WAIT peripheral function clock stop bit */
|
||
|
#define cm03 cm0_addr.bit.b3 /* Xcin-Xcout drive capacity select bit */
|
||
|
#define cm04 cm0_addr.bit.b4 /* Port Xc select bit */
|
||
|
#define cm05 cm0_addr.bit.b5 /* Main clock stop bit */
|
||
|
#define cm06 cm0_addr.bit.b6 /* WDT function select bit */
|
||
|
#define cm07 cm0_addr.bit.b7 /* CPU clock select bit0 */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
System clock control register 1
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def cm1_addr;
|
||
|
#define cm1 cm1_addr.byte
|
||
|
|
||
|
#define cm10 cm1_addr.bit.b0 /* All clock stop control bit */
|
||
|
/* (b4-b1) Reserved bit (Set to 0) */
|
||
|
/* (b5) Reserved bit (Set to 1) */
|
||
|
/* (b6) Reserved bit (Set to 0) */
|
||
|
#define cm17 cm1_addr.bit.b7 /* CPU clock select bit1 */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Oscillation stop detect register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def cm2_addr;
|
||
|
#define cm2 cm2_addr.byte
|
||
|
|
||
|
#define cm20 cm2_addr.bit.b0 /* Oscillation stop detect enable bit */
|
||
|
#define cm21 cm2_addr.bit.b1 /* CPU clock select bit2 */
|
||
|
#define cm22 cm2_addr.bit.b2 /* Oscillation stop detect flag */
|
||
|
#define cm23 cm2_addr.bit.b3 /* Main clock monitor flag */
|
||
|
/* (b7-b4) Reserved bit (Set to 0) */
|
||
|
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Address match interrupt enable register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def aier_addr;
|
||
|
#define aier aier_addr.byte
|
||
|
|
||
|
#define aier0 aier_addr.bit.b0 /* Address match interrupt 0 enable bit */
|
||
|
#define aier1 aier_addr.bit.b1 /* Address match interrupt 1 enable bit */
|
||
|
#define aier2 aier_addr.bit.b2 /* Address match interrupt 2 enable bit */
|
||
|
#define aier3 aier_addr.bit.b3 /* Address match interrupt 3 enable bit */
|
||
|
#define aier4 aier_addr.bit.b4 /* Address match interrupt 4 enable bit */
|
||
|
#define aier5 aier_addr.bit.b5 /* Address match interrupt 5 enable bit */
|
||
|
#define aier6 aier_addr.bit.b6 /* Address match interrupt 6 enable bit */
|
||
|
#define aier7 aier_addr.bit.b7 /* Address match interrupt 7 enable bit */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
X-Y control register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def xyc_addr;
|
||
|
#define xyc xyc_addr.byte
|
||
|
|
||
|
#define xyc0 xyc_addr.bit.b0 /* Read-mode set bit */
|
||
|
#define xyc1 xyc_addr.bit.b1 /* Write-mode set bit */
|
||
|
/* (b7-b2) Nothing is assigned */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Protect register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def prcr_addr;
|
||
|
#define prcr prcr_addr.byte
|
||
|
|
||
|
#define prc0 prcr_addr.bit.b0 /* Protect bit0 */
|
||
|
#define prc1 prcr_addr.bit.b1 /* Protect bit1 */
|
||
|
#define prc2 prcr_addr.bit.b2 /* Protect bit2 */
|
||
|
#define prc3 prcr_addr.bit.b3 /* Protect bit3 */
|
||
|
/* (b7-b4) Nothing is assigned */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
External data bus width control register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def ds_addr;
|
||
|
#define ds ds_addr.byte
|
||
|
|
||
|
#define ds0 ds_addr.bit.b0 /* External space 0 data bus width select bit */
|
||
|
#define ds1 ds_addr.bit.b1 /* External space 1 data bus width select bit */
|
||
|
#define ds2 ds_addr.bit.b2 /* External space 2 data bus width select bit */
|
||
|
#define ds3 ds_addr.bit.b3 /* External space 3 data bus width select bit */
|
||
|
/* (b7-b4) Nothing is assigned */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Main clock division register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def mcd_addr;
|
||
|
#define mcd mcd_addr.byte
|
||
|
|
||
|
#define mcd0 mcd_addr.bit.b0 /* (b4-b0) Main clock division select bit */
|
||
|
#define mcd1 mcd_addr.bit.b1
|
||
|
#define mcd2 mcd_addr.bit.b2
|
||
|
#define mcd3 mcd_addr.bit.b3
|
||
|
#define mcd4 mcd_addr.bit.b4
|
||
|
/* (b7-b5) Reserved bit (Set to 0) */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Count source prescaler register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def tcspr_addr;
|
||
|
#define tcspr tcspr_addr.byte
|
||
|
|
||
|
#define cnt0 tcspr_addr.bit.b0 /* (b3-b0) Divide ratio select bit */
|
||
|
#define cnt1 tcspr_addr.bit.b1
|
||
|
#define cnt2 tcspr_addr.bit.b2
|
||
|
#define cnt3 tcspr_addr.bit.b3
|
||
|
/* (b6-b4) Reserved bit (Set to 0) */
|
||
|
#define cst tcspr_addr.bit.b7 /* Operation enable bit */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
Exit priority register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def rlvl_addr;
|
||
|
#define rlvl rlvl_addr.byte
|
||
|
|
||
|
#define rlvl0 rlvl_addr.bit.b0 /* (b2-b0) Interrupt priority set bits to exit STOP/WAIT mode */
|
||
|
#define rlvl1 rlvl_addr.bit.b1
|
||
|
#define rlvl2 rlvl_addr.bit.b2
|
||
|
#define fsit rlvl_addr.bit.b3 /* High-speed interrupt set bit */
|
||
|
/* (b4) Nothing is assigned */
|
||
|
#define dmaii rlvl_addr.bit.b5 /* DMAC II select bit */
|
||
|
/* (b7-b6) Nothing is assigned */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
External interrupt request cause select register 1
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def ifsra_addr;
|
||
|
#define ifsra ifsra_addr.byte
|
||
|
|
||
|
#define ifsr10 ifsra_addr.bit.b0 /* INT6 interrupt polarity select bit */
|
||
|
#define ifsr11 ifsra_addr.bit.b1 /* INT7 interrupt polarity select bit */
|
||
|
#define ifsr12 ifsra_addr.bit.b2 /* INT8 interrupt polarity select bit */
|
||
|
/* (b7-b3) Reserved bit (Set to 0) */
|
||
|
|
||
|
/*------------------------------------------------------
|
||
|
External interrupt request cause select register
|
||
|
------------------------------------------------------*/
|
||
|
union byte_def ifsr_addr;
|
||
|
#define ifsr ifsr_addr.byte
|
||
Formats disponibles : Unified diff
Mise en place branche M.DEMAGALHAES