Révision 699
Ajouté par anclaud il y a presque 4 ans
| branch/CLAUD/sp4b3/SP4b3/sect308.inc | ||
|---|---|---|
|
;*******************************************************************************
|
||
|
;
|
||
|
; C Compiler for M16C/80
|
||
|
; Copyright (C) 1999 (2000 - 2010) Renesas Electronics Corporation.
|
||
|
; and Renesas Solutions Corporation. All rights reserved.
|
||
|
;
|
||
|
;
|
||
|
; sect30.inc : section definition
|
||
|
; This program is applicable when using the basic I/O library
|
||
|
;
|
||
|
; $Date: 2005/10/12 07:54:36 $
|
||
|
; $Revision: 1.24 $
|
||
|
;
|
||
|
;******************************************************************************
|
||
|
;---------------------------------------------------------------
|
||
|
;
|
||
|
; Arrangement of section
|
||
|
;
|
||
|
;---------------------------------------------------------------
|
||
|
; Near RAM data area
|
||
|
;---------------------------------------------------------------
|
||
|
; SBDATA area
|
||
|
.section data_SE,DATA
|
||
|
.org 400H
|
||
|
data_SE_top:
|
||
|
; for NSD
|
||
|
.section data_MON1_SE,DATA
|
||
|
data_MON1_SE_top:
|
||
|
.section data_MON2_SE,DATA
|
||
|
data_MON2_SE_top:
|
||
|
.section data_MON3_SE,DATA
|
||
|
data_MON3_SE_top:
|
||
|
.section data_MON4_SE,DATA
|
||
|
data_MON4_SE_top:
|
||
|
|
||
|
.section bss_SE,DATA,ALIGN
|
||
|
bss_SE_top:
|
||
|
; for NSD
|
||
|
.section bss_MON1_SE,DATA,ALIGN
|
||
|
bss_MON1_SE_top:
|
||
|
.section bss_MON2_SE,DATA,ALIGN
|
||
|
bss_MON2_SE_top:
|
||
|
.section bss_MON3_SE,DATA,ALIGN
|
||
|
bss_MON3_SE_top:
|
||
|
.section bss_MON4_SE,DATA,ALIGN
|
||
|
bss_MON4_SE_top:
|
||
|
|
||
|
.section data_SO,DATA
|
||
|
data_SO_top:
|
||
|
; for NSD
|
||
|
.section data_MON1_SO,DATA
|
||
|
data_MON1_SO_top:
|
||
|
.section data_MON2_SO,DATA
|
||
|
data_MON2_SO_top:
|
||
|
.section data_MON3_SO,DATA
|
||
|
data_MON3_SO_top:
|
||
|
.section data_MON4_SO,DATA
|
||
|
data_MON4_SO_top:
|
||
|
|
||
|
.section bss_SO,DATA
|
||
|
bss_SO_top:
|
||
|
; for NSD
|
||
|
.section bss_MON1_SO,DATA
|
||
|
bss_MON1_SO_top:
|
||
|
.section bss_MON2_SO,DATA
|
||
|
bss_MON2_SO_top:
|
||
|
.section bss_MON3_SO,DATA
|
||
|
bss_MON3_SO_top:
|
||
|
.section bss_MON4_SO,DATA
|
||
|
bss_MON4_SO_top:
|
||
|
|
||
|
; near RAM area
|
||
|
.section data_NE,DATA,ALIGN
|
||
|
data_NE_top:
|
||
|
; for NSD
|
||
|
.section data_MON1_E,DATA,ALIGN
|
||
|
data_MON1_E_top:
|
||
|
.section data_MON2_E,DATA,ALIGN
|
||
|
data_MON2_E_top:
|
||
|
.section data_MON3_E,DATA,ALIGN
|
||
|
data_MON3_E_top:
|
||
|
.section data_MON4_E,DATA,ALIGN
|
||
|
data_MON4_E_top:
|
||
|
|
||
|
.section bss_NE,DATA,ALIGN
|
||
|
bss_NE_top:
|
||
|
; for NSD
|
||
|
.section bss_MON1_E,DATA,ALIGN
|
||
|
bss_MON1_E_top:
|
||
|
.section bss_MON2_E,DATA,ALIGN
|
||
|
bss_MON2_E_top:
|
||
|
.section bss_MON3_E,DATA,ALIGN
|
||
|
bss_MON3_E_top:
|
||
|
.section bss_MON4_E,DATA,ALIGN
|
||
|
bss_MON4_E_top:
|
||
|
|
||
|
.section data_NO,DATA
|
||
|
data_NO_top:
|
||
|
; for NSD
|
||
|
.section data_MON1_O,DATA
|
||
|
data_MON1_O_top:
|
||
|
.section data_MON2_O,DATA
|
||
|
data_MON2_O_top:
|
||
|
.section data_MON3_O,DATA
|
||
|
data_MON3_O_top:
|
||
|
.section data_MON4_O,DATA
|
||
|
data_MON4_O_top:
|
||
|
|
||
|
.section bss_NO,DATA
|
||
|
bss_NO_top:
|
||
|
; for NSD
|
||
|
.section bss_MON1_O,DATA
|
||
|
bss_MON1_O_top:
|
||
|
.section bss_MON2_O,DATA
|
||
|
bss_MON2_O_top:
|
||
|
.section bss_MON3_O,DATA
|
||
|
bss_MON3_O_top:
|
||
|
.section bss_MON4_O,DATA
|
||
|
bss_MON4_O_top:
|
||
|
|
||
|
;---------------------------------------------------------------
|
||
|
; Stack area
|
||
|
;---------------------------------------------------------------
|
||
|
.section stack,DATA,ALIGN
|
||
|
.blkb STACKSIZE
|
||
|
.align
|
||
|
stack_top:
|
||
|
|
||
|
.blkb ISTACKSIZE
|
||
|
.align
|
||
|
istack_top:
|
||
|
|
||
|
|
||
|
;---------------------------------------------------------------
|
||
|
; heap section
|
||
|
;---------------------------------------------------------------
|
||
|
.if __HEAP__ != 1
|
||
|
.section heap,DATA
|
||
|
heap_top:
|
||
|
.blkb HEAPSIZE
|
||
|
.endif
|
||
|
|
||
|
;---------------------------------------------------------------
|
||
|
; Near ROM data area
|
||
|
;---------------------------------------------------------------
|
||
|
.section rom_NE,ROMDATA,ALIGN
|
||
|
rom_NE_top:
|
||
|
|
||
|
.section rom_NO,ROMDATA
|
||
|
rom_NO_top:
|
||
|
|
||
|
;---------------------------------------------------------------
|
||
|
; Far RAM data area
|
||
|
;---------------------------------------------------------------
|
||
|
; SBDATA area for #pragma SB16DATA
|
||
|
; .section data_SE,DATA
|
||
|
; .org 10000H
|
||
|
;data_SE_top:
|
||
|
; for NSD
|
||
|
; .section data_MON1_SE,DATA
|
||
|
;data_MON1_SE_top:
|
||
|
; .section data_MON2_SE,DATA
|
||
|
;data_MON2_SE_top:
|
||
|
; .section data_MON3_SE,DATA
|
||
|
;data_MON3_SE_top:
|
||
|
; .section data_MON4_SE,DATA
|
||
|
;data_MON4_SE_top:
|
||
|
;
|
||
|
; .section bss_SE,DATA,ALIGN
|
||
|
;bss_SE_top:
|
||
|
; for NSD
|
||
|
; .section bss_MON1_SE,DATA,ALIGN
|
||
|
;bss_MON1_SE_top:
|
||
|
; .section bss_MON2_SE,DATA,ALIGN
|
||
|
;bss_MON2_SE_top:
|
||
|
; .section bss_MON3_SE,DATA,ALIGN
|
||
|
;bss_MON3_SE_top:
|
||
|
; .section bss_MON4_SE,DATA,ALIGN
|
||
|
;bss_MON4_SE_top:
|
||
|
;
|
||
|
; .section data_SO,DATA
|
||
|
;data_SO_top:
|
||
|
; for NSD
|
||
|
; .section data_MON1_SO,DATA
|
||
|
;data_MON1_SO_top:
|
||
|
; .section data_MON2_SO,DATA
|
||
|
;data_MON2_SO_top:
|
||
|
; .section data_MON3_SO,DATA
|
||
|
;data_MON3_SO_top:
|
||
|
; .section data_MON4_SO,DATA
|
||
|
;data_MON4_SO_top:
|
||
|
;
|
||
|
; .section bss_SO,DATA
|
||
|
;bss_SO_top:
|
||
|
; for NSD
|
||
|
; .section bss_MON1_SO,DATA
|
||
|
;bss_MON1_SO_top:
|
||
|
; .section bss_MON2_SO,DATA
|
||
|
;bss_MON2_SO_top:
|
||
|
; .section bss_MON3_SO,DATA
|
||
|
;bss_MON3_SO_top:
|
||
|
; .section bss_MON4_SO,DATA
|
||
|
;bss_MON4_SO_top:
|
||
|
;
|
||
|
; .section data_6E,DATA,ALIGN
|
||
|
;data_6E_top:
|
||
|
; for NSD
|
||
|
; .section data_MON1_6E,DATA,ALIGN
|
||
|
;data_MON1_6E_top:
|
||
|
; .section data_MON2_6E,DATA,ALIGN
|
||
|
;data_MON2_6E_top:
|
||
|
; .section data_MON3_6E,DATA,ALIGN
|
||
|
;data_MON3_6E_top:
|
||
|
; .section data_MON4_6E,DATA,ALIGN
|
||
|
;data_MON4_6E_top:
|
||
|
;
|
||
|
; .section bss_6E,DATA,ALIGN
|
||
|
;bss_6E_top:
|
||
|
; for NSD
|
||
|
; .section bss_MON1_6E,DATA,ALIGN
|
||
|
;bss_MON1_6E_top:
|
||
|
; .section bss_MON2_6E,DATA,ALIGN
|
||
|
;bss_MON2_6E_top:
|
||
|
; .section bss_MON3_6E,DATA,ALIGN
|
||
|
;bss_MON3_6E_top:
|
||
|
; .section bss_MON4_6E,DATA,ALIGN
|
||
|
;bss_MON4_6E_top:
|
||
|
;
|
||
|
; .section data_6O,DATA
|
||
|
;data_6O_top:
|
||
|
; for NSD
|
||
|
; .section data_MON1_6O,DATA
|
||
|
;data_MON1_6O_top:
|
||
|
; .section data_MON2_6O,DATA
|
||
|
;data_MON2_6O_top:
|
||
|
; .section data_MON3_6O,DATA
|
||
|
;data_MON3_6O_top:
|
||
|
; .section data_MON4_6O,DATA
|
||
|
;data_MON4_6O_top:
|
||
|
;
|
||
|
; .section bss_6O,DATA
|
||
|
;bss_6O_top:
|
||
|
; for NSD
|
||
|
; .section bss_MON1_6O,DATA
|
||
|
;bss_MON1_6O_top:
|
||
|
; .section bss_MON2_6O,DATA
|
||
|
;bss_MON2_6O_top:
|
||
|
; .section bss_MON3_6O,DATA
|
||
|
;bss_MON3_6O_top:
|
||
|
; .section bss_MON4_6O,DATA
|
||
|
;bss_MON4_6O_top:
|
||
|
;
|
||
|
.section data_FE,DATA
|
||
|
.org 20000H
|
||
|
data_FE_top:
|
||
|
; for NSD
|
||
|
; .section data_MON1_E,DATA
|
||
|
;data_MON1_E_top:
|
||
|
; .section data_MON2_E,DATA
|
||
|
;data_MON2_E_top:
|
||
|
; .section data_MON3_E,DATA
|
||
|
;data_MON3_E_top:
|
||
|
; .section data_MON4_E,DATA
|
||
|
;data_MON4_E_top:
|
||
|
|
||
|
.section bss_FE,DATA,ALIGN
|
||
|
bss_FE_top:
|
||
|
; for NSD
|
||
|
; .section bss_MON1_E,DATA,ALIGN
|
||
|
;bss_MON1_E_top:
|
||
|
; .section bss_MON2_E,DATA,ALIGN
|
||
|
;bss_MON2_E_top:
|
||
|
; .section bss_MON3_E,DATA,ALIGN
|
||
|
;bss_MON3_E_top:
|
||
|
; .section bss_MON4_E,DATA,ALIGN
|
||
|
;bss_MON4_E_top:
|
||
|
|
||
|
.section data_FO,DATA
|
||
|
data_FO_top:
|
||
|
; for NSD
|
||
|
; .section data_MON1_O,DATA
|
||
|
;data_MON1_O_top:
|
||
|
; .section data_MON2_O,DATA
|
||
|
;data_MON2_O_top:
|
||
|
; .section data_MON3_O,DATA
|
||
|
;data_MON3_O_top:
|
||
|
; .section data_MON4_O,DATA
|
||
|
;data_MON4_O_top:
|
||
|
|
||
|
.section bss_FO,DATA
|
||
|
bss_FO_top:
|
||
|
; for NSD
|
||
|
; .section bss_MON1_O,DATA
|
||
|
;bss_MON1_O_top:
|
||
|
; .section bss_MON2_O,DATA
|
||
|
;bss_MON2_O_top:
|
||
|
; .section bss_MON3_O,DATA
|
||
|
;bss_MON3_O_top:
|
||
|
; .section bss_MON4_O,DATA
|
||
|
;bss_MON4_O_top:
|
||
|
|
||
|
|
||
|
;---------------------------------------------------------------
|
||
|
; Far ROM data area
|
||
|
;---------------------------------------------------------------
|
||
|
.section rom_FE,ROMDATA
|
||
|
.org 0FE0000H
|
||
|
rom_FE_top:
|
||
|
|
||
|
.section rom_FO,ROMDATA
|
||
|
rom_FO_top:
|
||
|
|
||
|
;---------------------------------------------------------------
|
||
|
; Initial data of 'data' section
|
||
|
;---------------------------------------------------------------
|
||
|
.section data_SEI,ROMDATA
|
||
|
data_SEI_top:
|
||
|
; for NSD
|
||
|
.section data_MON1_SEI,ROMDATA
|
||
|
data_MON1_SEI_top:
|
||
|
.section data_MON2_SEI,ROMDATA
|
||
|
data_MON2_SEI_top:
|
||
|
.section data_MON3_SEI,ROMDATA
|
||
|
data_MON3_SEI_top:
|
||
|
.section data_MON4_SEI,ROMDATA
|
||
|
data_MON4_SEI_top:
|
||
|
|
||
|
.section data_SOI,ROMDATA
|
||
|
data_SOI_top:
|
||
|
; for NSD
|
||
|
.section data_MON1_SOI,ROMDATA
|
||
|
data_MON1_SOI_top:
|
||
|
.section data_MON2_SOI,ROMDATA
|
||
|
data_MON2_SOI_top:
|
||
|
.section data_MON3_SOI,ROMDATA
|
||
|
data_MON3_SOI_top:
|
||
|
.section data_MON4_SOI,ROMDATA
|
||
|
data_MON4_SOI_top:
|
||
|
|
||
|
; .section data_6EI,ROMDATA
|
||
|
;data_6EI_top:
|
||
|
; for NSD
|
||
|
; .section data_MON1_6EI,ROMDATA
|
||
|
;data_MON1_6EI_top:
|
||
|
; .section data_MON2_6EI,ROMDATA
|
||
|
;data_MON2_6EI_top:
|
||
|
; .section data_MON3_6EI,ROMDATA
|
||
|
;data_MON3_6EI_top:
|
||
|
; .section data_MON4_6EI,ROMDATA
|
||
|
;data_MON4_6EI_top:
|
||
|
;
|
||
|
; .section data_6OI,ROMDATA
|
||
|
;data_6OI_top:
|
||
|
; for NSD
|
||
|
; .section data_MON1_6OI,ROMDATA
|
||
|
;data_MON1_6OI_top:
|
||
|
; .section data_MON2_6OI,ROMDATA
|
||
|
;data_MON2_6OI_top:
|
||
|
; .section data_MON3_6OI,ROMDATA
|
||
|
;data_MON3_6OI_top:
|
||
|
; .section data_MON4_6OI,ROMDATA
|
||
|
;data_MON4_6OI_top:
|
||
|
|
||
|
.section data_NEI,ROMDATA
|
||
|
data_NEI_top:
|
||
|
; for NSD
|
||
|
.section data_MON1_EI,ROMDATA
|
||
|
data_MON1_EI_top:
|
||
|
.section data_MON2_EI,ROMDATA
|
||
|
data_MON2_EI_top:
|
||
|
.section data_MON3_EI,ROMDATA
|
||
|
data_MON3_EI_top:
|
||
|
.section data_MON4_EI,ROMDATA
|
||
|
data_MON4_EI_top:
|
||
|
|
||
|
.section data_NOI,ROMDATA
|
||
|
data_NOI_top:
|
||
|
; for NSD
|
||
|
.section data_MON1_OI,ROMDATA
|
||
|
data_MON1_OI_top:
|
||
|
.section data_MON2_OI,ROMDATA
|
||
|
data_MON2_OI_top:
|
||
|
.section data_MON3_OI,ROMDATA
|
||
|
data_MON3_OI_top:
|
||
|
.section data_MON4_OI,ROMDATA
|
||
|
data_MON4_OI_top:
|
||
|
|
||
|
.section data_FEI,ROMDATA
|
||
|
data_FEI_top:
|
||
|
; for NSD
|
||
|
; .section data_MON1_EI,ROMDATA
|
||
|
;data_MON1_EI_top:
|
||
|
; .section data_MON2_EI,ROMDATA
|
||
|
;data_MON2_EI_top:
|
||
|
; .section data_MON3_EI,ROMDATA
|
||
|
;data_MON3_EI_top:
|
||
|
; .section data_MON4_EI,ROMDATA
|
||
|
;data_MON4_EI_top:
|
||
|
|
||
|
.section data_FOI,ROMDATA
|
||
|
data_FOI_top:
|
||
|
; for NSD
|
||
|
; .section data_MON1_OI,ROMDATA
|
||
|
;data_MON1_OI_top:
|
||
|
; .section data_MON2_OI,ROMDATA
|
||
|
;data_MON2_OI_top:
|
||
|
; .section data_MON3_OI,ROMDATA
|
||
|
;data_MON3_OI_top:
|
||
|
; .section data_MON4_OI,ROMDATA
|
||
|
;data_MON4_OI_top:
|
||
|
|
||
|
;---------------------------------------------------------------
|
||
|
; code area
|
||
|
;---------------------------------------------------------------
|
||
|
.section interrupt,ALIGN
|
||
|
|
||
|
.section program,ALIGN
|
||
|
|
||
|
.section program_S
|
||
|
.org 0FF0000H
|
||
|
|
||
|
|
||
|
;---------------------------------------------------------------
|
||
|
; variable vector section
|
||
|
;---------------------------------------------------------------
|
||
|
.section vector,ROMDATA ; variable vector table
|
||
|
.org VECTOR_ADR
|
||
|
.if __MVT__ == 0
|
||
|
.lword dummy_int ; BRK (software int 0)
|
||
|
.lword dummy_int ;
|
||
|
.lword dummy_int ;
|
||
|
.lword dummy_int ;
|
||
|
.lword dummy_int ;
|
||
|
.lword dummy_int ;
|
||
|
.lword dummy_int ;
|
||
|
.lword dummy_int ;
|
||
|
.lword dummy_int ; DMA0 (software int 8)
|
||
|
.lword dummy_int ; DMA1 (software int 9)
|
||
|
.lword dummy_int ; DMA2 (software int 10)
|
||
|
.lword dummy_int ; DMA3 (software int 11)
|
||
|
.lword dummy_int ; TIMER A0 (software int 12)
|
||
|
.lword dummy_int ; TIMER A1 (software int 13)
|
||
|
.lword dummy_int ; TIMER A2 (software int 14)
|
||
|
.lword dummy_int ; TIMER A3 (software int 15)
|
||
|
.lword dummy_int ; TIMER A4 (software int 16)
|
||
|
.lword dummy_int ; uart0 trance (software int 17)
|
||
|
.lword dummy_int ; uart0 receive (software int 18)
|
||
|
.lword dummy_int ; uart1 trance (software int 19)
|
||
|
.lword dummy_int ; uart1 receive (software int 20)
|
||
|
.lword dummy_int ; TIMER B0 (software int 21)
|
||
|
.lword dummy_int ; TIMER B1 (software int 22)
|
||
|
.lword dummy_int ; TIMER B2 (software int 23)
|
||
|
.lword dummy_int ; TIMER B3 (software int 24)
|
||
|
.lword dummy_int ; TIMER B4 (software int 25)
|
||
|
.lword dummy_int ; INT5 (software int 26)
|
||
|
.lword dummy_int ; INT4 (software int 27)
|
||
|
.lword dummy_int ; INT3 (software int 28)
|
||
|
.lword dummy_int ; INT2 (software int 29)
|
||
|
.lword dummy_int ; INT1 (software int 30)
|
||
|
.lword dummy_int ; INT0 (software int 31)
|
||
|
.lword dummy_int ; TIMER B5 (software int 32)
|
||
|
.lword dummy_int ; uart2 trance/NACK (software int 33)
|
||
|
.lword dummy_int ; uart2 receive/ACK (software int 34)
|
||
|
.lword dummy_int ; uart3 trance/NACK (software int 35)
|
||
|
.lword dummy_int ; uart3 receive/ACK (software int 36)
|
||
|
.lword dummy_int ; uart4 trance/NACK (software int 37)
|
||
|
.lword dummy_int ; uart4 receive/ACK (software int 38)
|
||
|
.lword dummy_int ; uart2 bus collision (software int 39)
|
||
|
.lword dummy_int ; uart3 bus collision (software int 40)
|
||
|
.lword dummy_int ; uart4 bus collision (software int 41)
|
||
|
.lword dummy_int ; A-D Convert (software int 42)
|
||
|
.lword dummy_int ; input key (software int 43)
|
||
|
.lword dummy_int ; software int 44
|
||
|
.lword dummy_int ; software int 45
|
||
|
.lword dummy_int ; software int 46
|
||
|
.lword dummy_int ; software int 47
|
||
|
.lword dummy_int ; software int 48
|
||
|
.lword dummy_int ; software int 49
|
||
|
.lword dummy_int ; software int 50
|
||
|
.lword dummy_int ; software int 51
|
||
|
.lword dummy_int ; software int 52
|
||
|
.lword dummy_int ; software int 53
|
||
|
.lword dummy_int ; software int 54
|
||
|
.lword dummy_int ; software int 55
|
||
|
.lword dummy_int ; software int 56
|
||
|
.lword dummy_int ; software int 57
|
||
|
.lword dummy_int ; software int 58
|
||
|
.lword dummy_int ; software int 59
|
||
|
.lword dummy_int ; software int 60
|
||
|
.lword dummy_int ; software int 61
|
||
|
.lword dummy_int ; software int 62
|
||
|
.lword dummy_int ; software int 63
|
||
|
.endif ; __MVT__
|
||
|
|
||
|
|
||
|
;===============================================================
|
||
|
; fixed vector section
|
||
|
;---------------------------------------------------------------
|
||
|
.section svector,ROMDATA ; specialpage vector table
|
||
|
.if __MST__ == 0
|
||
|
.org SVECTOR_ADR
|
||
|
;===============================================================
|
||
|
; special page defination
|
||
|
;---------------------------------------------------------------
|
||
|
; macro is defined in ncrt0.a30
|
||
|
; Format: SPECIAL number
|
||
|
;
|
||
|
;---------------------------------------------------------------
|
||
|
; SPECIAL 255
|
||
|
; SPECIAL 254
|
||
|
; SPECIAL 253
|
||
|
; SPECIAL 252
|
||
|
; SPECIAL 251
|
||
|
; SPECIAL 250
|
||
|
; SPECIAL 249
|
||
|
; SPECIAL 248
|
||
|
; SPECIAL 247
|
||
|
; SPECIAL 246
|
||
|
; SPECIAL 245
|
||
|
; SPECIAL 244
|
||
|
; SPECIAL 243
|
||
|
; SPECIAL 242
|
||
|
; SPECIAL 241
|
||
|
; SPECIAL 240
|
||
|
; SPECIAL 239
|
||
|
; SPECIAL 238
|
||
|
; SPECIAL 237
|
||
|
; SPECIAL 236
|
||
|
; SPECIAL 235
|
||
|
; SPECIAL 234
|
||
|
; SPECIAL 233
|
||
|
; SPECIAL 232
|
||
|
; SPECIAL 231
|
||
|
; SPECIAL 230
|
||
|
; SPECIAL 229
|
||
|
; SPECIAL 228
|
||
|
; SPECIAL 227
|
||
|
; SPECIAL 226
|
||
|
; SPECIAL 225
|
||
|
; SPECIAL 224
|
||
|
; SPECIAL 223
|
||
|
; SPECIAL 222
|
||
|
; SPECIAL 221
|
||
|
; SPECIAL 220
|
||
|
; SPECIAL 219
|
||
|
; SPECIAL 218
|
||
|
; SPECIAL 217
|
||
|
; SPECIAL 216
|
||
|
; SPECIAL 215
|
||
|
; SPECIAL 214
|
||
|
; SPECIAL 213
|
||
|
; SPECIAL 212
|
||
|
; SPECIAL 211
|
||
|
; SPECIAL 210
|
||
|
; SPECIAL 209
|
||
|
; SPECIAL 208
|
||
|
; SPECIAL 207
|
||
|
; SPECIAL 206
|
||
|
; SPECIAL 205
|
||
|
; SPECIAL 204
|
||
|
; SPECIAL 203
|
||
|
; SPECIAL 202
|
||
|
; SPECIAL 201
|
||
|
; SPECIAL 200
|
||
|
; SPECIAL 199
|
||
|
; SPECIAL 198
|
||
|
; SPECIAL 197
|
||
|
; SPECIAL 196
|
||
|
; SPECIAL 195
|
||
|
; SPECIAL 194
|
||
|
; SPECIAL 193
|
||
|
; SPECIAL 192
|
||
|
; SPECIAL 191
|
||
|
; SPECIAL 190
|
||
|
; SPECIAL 189
|
||
|
; SPECIAL 188
|
||
|
; SPECIAL 187
|
||
|
; SPECIAL 186
|
||
|
; SPECIAL 185
|
||
|
; SPECIAL 184
|
||
|
; SPECIAL 183
|
||
|
; SPECIAL 182
|
||
|
; SPECIAL 181
|
||
|
; SPECIAL 180
|
||
|
; SPECIAL 179
|
||
|
; SPECIAL 178
|
||
|
; SPECIAL 177
|
||
|
; SPECIAL 176
|
||
|
; SPECIAL 175
|
||
|
; SPECIAL 174
|
||
|
; SPECIAL 173
|
||
|
; SPECIAL 172
|
||
|
; SPECIAL 171
|
||
|
; SPECIAL 170
|
||
|
; SPECIAL 169
|
||
|
; SPECIAL 168
|
||
|
; SPECIAL 167
|
||
|
; SPECIAL 166
|
||
|
; SPECIAL 165
|
||
|
; SPECIAL 164
|
||
|
; SPECIAL 163
|
||
|
; SPECIAL 162
|
||
|
; SPECIAL 161
|
||
|
; SPECIAL 160
|
||
|
; SPECIAL 159
|
||
|
; SPECIAL 158
|
||
|
; SPECIAL 157
|
||
|
; SPECIAL 156
|
||
|
; SPECIAL 155
|
||
|
; SPECIAL 154
|
||
|
; SPECIAL 153
|
||
|
; SPECIAL 152
|
||
|
; SPECIAL 151
|
||
|
; SPECIAL 150
|
||
|
; SPECIAL 149
|
||
|
; SPECIAL 148
|
||
|
; SPECIAL 147
|
||
|
; SPECIAL 146
|
||
|
; SPECIAL 145
|
||
|
; SPECIAL 144
|
||
|
; SPECIAL 143
|
||
|
; SPECIAL 142
|
||
|
; SPECIAL 141
|
||
|
; SPECIAL 140
|
||
|
; SPECIAL 139
|
||
|
; SPECIAL 138
|
||
|
; SPECIAL 137
|
||
|
; SPECIAL 136
|
||
|
; SPECIAL 135
|
||
|
; SPECIAL 134
|
||
|
; SPECIAL 133
|
||
|
; SPECIAL 132
|
||
|
; SPECIAL 131
|
||
|
; SPECIAL 130
|
||
|
; SPECIAL 129
|
||
|
; SPECIAL 128
|
||
|
; SPECIAL 127
|
||
|
; SPECIAL 126
|
||
|
; SPECIAL 125
|
||
|
; SPECIAL 124
|
||
|
; SPECIAL 123
|
||
|
; SPECIAL 122
|
||
|
; SPECIAL 121
|
||
|
; SPECIAL 120
|
||
|
; SPECIAL 119
|
||
|
; SPECIAL 118
|
||
|
; SPECIAL 117
|
||
|
; SPECIAL 116
|
||
|
; SPECIAL 115
|
||
|
; SPECIAL 114
|
||
|
; SPECIAL 113
|
||
|
; SPECIAL 112
|
||
|
; SPECIAL 111
|
||
|
; SPECIAL 110
|
||
|
; SPECIAL 109
|
||
|
; SPECIAL 108
|
||
|
; SPECIAL 107
|
||
|
; SPECIAL 106
|
||
|
; SPECIAL 105
|
||
|
; SPECIAL 104
|
||
|
; SPECIAL 103
|
||
|
; SPECIAL 102
|
||
|
; SPECIAL 101
|
||
|
; SPECIAL 100
|
||
|
; SPECIAL 99
|
||
|
; SPECIAL 98
|
||
|
; SPECIAL 97
|
||
|
; SPECIAL 96
|
||
|
; SPECIAL 95
|
||
|
; SPECIAL 94
|
||
|
; SPECIAL 93
|
||
|
; SPECIAL 92
|
||
|
; SPECIAL 91
|
||
|
; SPECIAL 90
|
||
|
; SPECIAL 89
|
||
|
; SPECIAL 88
|
||
|
; SPECIAL 87
|
||
|
; SPECIAL 86
|
||
|
; SPECIAL 85
|
||
|
; SPECIAL 84
|
||
|
; SPECIAL 83
|
||
|
; SPECIAL 82
|
||
|
; SPECIAL 81
|
||
|
; SPECIAL 80
|
||
|
; SPECIAL 79
|
||
|
; SPECIAL 78
|
||
|
; SPECIAL 77
|
||
|
; SPECIAL 76
|
||
|
; SPECIAL 75
|
||
|
; SPECIAL 74
|
||
|
; SPECIAL 73
|
||
|
; SPECIAL 72
|
||
|
; SPECIAL 71
|
||
|
; SPECIAL 70
|
||
|
; SPECIAL 69
|
||
|
; SPECIAL 68
|
||
|
; SPECIAL 67
|
||
|
; SPECIAL 66
|
||
|
; SPECIAL 65
|
||
|
; SPECIAL 64
|
||
|
; SPECIAL 63
|
||
|
; SPECIAL 62
|
||
|
; SPECIAL 61
|
||
|
; SPECIAL 60
|
||
|
; SPECIAL 59
|
||
|
; SPECIAL 58
|
||
|
; SPECIAL 57
|
||
|
; SPECIAL 56
|
||
|
; SPECIAL 55
|
||
|
; SPECIAL 54
|
||
|
; SPECIAL 53
|
||
|
; SPECIAL 52
|
||
|
; SPECIAL 51
|
||
|
; SPECIAL 50
|
||
|
; SPECIAL 49
|
||
|
; SPECIAL 48
|
||
|
; SPECIAL 47
|
||
|
; SPECIAL 46
|
||
|
; SPECIAL 45
|
||
|
; SPECIAL 44
|
||
|
; SPECIAL 43
|
||
|
; SPECIAL 42
|
||
|
; SPECIAL 41
|
||
|
; SPECIAL 40
|
||
|
; SPECIAL 39
|
||
|
; SPECIAL 38
|
||
|
; SPECIAL 37
|
||
|
; SPECIAL 36
|
||
|
; SPECIAL 35
|
||
|
; SPECIAL 34
|
||
|
; SPECIAL 33
|
||
|
; SPECIAL 32
|
||
|
; SPECIAL 31
|
||
|
; SPECIAL 30
|
||
|
; SPECIAL 29
|
||
|
; SPECIAL 28
|
||
|
; SPECIAL 27
|
||
|
; SPECIAL 26
|
||
|
; SPECIAL 25
|
||
|
; SPECIAL 24
|
||
|
; SPECIAL 23
|
||
|
; SPECIAL 22
|
||
|
; SPECIAL 21
|
||
|
; SPECIAL 20
|
||
|
; SPECIAL 19
|
||
|
; SPECIAL 18
|
||
|
;
|
||
|
.endif ; __MST__
|
||
|
|
||
|
|
||
|
;===============================================================
|
||
|
; fixed vector section
|
||
|
;---------------------------------------------------------------
|
||
|
.section fvector,ROMDATA
|
||
|
.org 0FFFFDCh
|
||
|
UDI:
|
||
|
.lword dummy_int
|
||
|
OVER_FLOW:
|
||
|
.lword dummy_int
|
||
|
BRKI:
|
||
|
.lword dummy_int
|
||
|
ADDRESS_MATCH:
|
||
|
.lword dummy_int
|
||
|
SINGLE_STEP:
|
||
|
.lword dummy_int
|
||
|
WDT:
|
||
|
.lword dummy_int
|
||
|
DBC:
|
||
|
.lword dummy_int
|
||
|
NMI:
|
||
|
.lword dummy_int
|
||
|
RESET:
|
||
|
.lword start
|
||
|
;
|
||
|
;*******************************************************************************
|
||
|
;
|
||
|
; C Compiler for M16C/80
|
||
|
; Copyright (C) 1999 (2000 - 2010) Renesas Electronics Corporation.
|
||
|
; and Renesas Solutions Corporation. All rights reserved.
|
||
|
;
|
||
|
;
|
||
|
;*******************************************************************************
|
||
|
|
||
| branch/CLAUD/sp4b3/SP4b3/SessionM32C_Simulator.hsf | ||
|---|---|---|
|
[HIMDBVersion]
|
||
|
2.0
|
||
|
[DATABASE_VERSION]
|
||
|
"2.3"
|
||
|
[SESSION_DETAILS]
|
||
|
""
|
||
|
[INFORMATION]
|
||
|
""
|
||
|
[GENERAL_DATA]
|
||
|
"RESET_CPU_AFTER_DOWNLOAD_TAG" "VARIANT_TRUE_STORE_TAG"
|
||
|
[LANGUAGE]
|
||
|
"English"
|
||
|
[CONFIG_INFO_VD1]
|
||
|
0
|
||
|
[CONFIG_INFO_VD2]
|
||
|
0
|
||
|
[CONFIG_INFO_VD3]
|
||
|
0
|
||
|
[CONFIG_INFO_VD4]
|
||
|
0
|
||
|
[WINDOW_POSITION_STATE_DATA_VD1]
|
||
|
[WINDOW_POSITION_STATE_DATA_VD2]
|
||
|
[WINDOW_POSITION_STATE_DATA_VD3]
|
||
|
[WINDOW_POSITION_STATE_DATA_VD4]
|
||
|
[WINDOW_Z_ORDER]
|
||
|
[TARGET_NAME]
|
||
|
"M32C Simulator" "" 0
|
||
|
[STATUSBAR_STATEINFO_VD1]
|
||
|
"MasterShowState" 1
|
||
|
"ApplicationShowState" 1
|
||
|
"DebuggerShowState" 1
|
||
|
[STATUSBAR_STATEINFO_VD2]
|
||
|
"MasterShowState" 1
|
||
|
"ApplicationShowState" 1
|
||
|
"DebuggerShowState" 1
|
||
|
[STATUSBAR_STATEINFO_VD3]
|
||
|
"MasterShowState" 1
|
||
|
"ApplicationShowState" 1
|
||
|
"DebuggerShowState" 1
|
||
|
[STATUSBAR_STATEINFO_VD4]
|
||
|
"MasterShowState" 1
|
||
|
"ApplicationShowState" 1
|
||
|
"DebuggerShowState" 1
|
||
|
[STATUSBAR_DEBUGGER_PANESTATE_VD1]
|
||
|
[STATUSBAR_DEBUGGER_PANESTATE_VD2]
|
||
|
[STATUSBAR_DEBUGGER_PANESTATE_VD3]
|
||
|
[STATUSBAR_DEBUGGER_PANESTATE_VD4]
|
||
|
[DEBUGGER_OPTIONS]
|
||
|
"Unknown Options"
|
||
|
[DOWNLOAD_MODULES]
|
||
|
"$(CONFIGDIR)\$(PROJECTNAME).x30" 0 "IEEE695_RENESAS" 0 0 1 0
|
||
|
[CONNECT_ON_GO]
|
||
|
"FALSE"
|
||
|
[DOWNLOAD_MODULES_AFTER_BUILD]
|
||
|
"TRUE"
|
||
|
[REMOVE_BREAKPOINTS_ON_DOWNLOAD]
|
||
|
"TRUE"
|
||
|
[DISABLE_MEMORY_ACCESS_PRIOR_TO_COMMAND_FILE_EXECUTION]
|
||
|
"FALSE"
|
||
|
[LIMIT_DISASSEMBLY_MEMORY_ACCESS]
|
||
|
"FALSE"
|
||
|
[DISABLE_MEMORY_ACCESS_DURING_EXECUTION]
|
||
|
"FALSE"
|
||
|
[DEBUGGER_OPTIONS_PROPERTIES]
|
||
|
"1"
|
||
|
[COMMAND_FILES]
|
||
|
[DEFAULT_DEBUG_FORMAT]
|
||
|
""
|
||
|
[FLASH_DETAILS]
|
||
|
"" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" ""
|
||
|
[BREAKPOINTS]
|
||
|
[END]
|
||
| branch/CLAUD/sp4b3/SP4b3/DefaultSession.hsf | ||
|---|---|---|
|
[HIMDBVersion]
|
||
|
2.0
|
||
|
[DATABASE_VERSION]
|
||
|
"2.3"
|
||
|
[SESSION_DETAILS]
|
||
|
""
|
||
|
[INFORMATION]
|
||
|
""
|
||
|
[GENERAL_DATA]
|
||
|
"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlECX_MAP_FIND_SYMBOL_LIST" ""
|
||
|
"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0"
|
||
|
"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" ""
|
||
|
"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointFlag" "-1 "
|
||
|
"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointStatus" "-1 "
|
||
|
"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBrowseDirectory" ""
|
||
|
"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" ""
|
||
|
"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlSplitterPosition" "242"
|
||
|
"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "0"
|
||
|
"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" ""
|
||
|
"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileDir" ""
|
||
|
"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileName" ""
|
||
|
"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0"
|
||
|
[LANGUAGE]
|
||
|
"English"
|
||
|
[CONFIG_INFO_VD1]
|
||
|
1
|
||
|
[CONFIG_INFO_VD2]
|
||
|
0
|
||
|
[CONFIG_INFO_VD3]
|
||
|
0
|
||
|
[CONFIG_INFO_VD4]
|
||
|
0
|
||
|
[WINDOW_POSITION_STATE_DATA_VD1]
|
||
|
"Help" "TOOLBAR 0" 59419 1 5 "0.00" 0 0 0 0 0 17 0 "" "0.0"
|
||
|
"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 0 "1.00" 180 683 371 350 200 18 0 "36756|36757|36758|36759|<<separator>>|36746|36747|<<separator>>|39531|<<separator>>|39500|39534|<<separator>>|36687" "0.0"
|
||
|
"{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 180 683 371 350 200 18 0 "" "0.0"
|
||
|
"{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0"
|
||
|
"{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0"
|
||
|
"{WK_TB00000003_BOOKMARKS}" "TOOLBAR 0" 59419 1 1 "0.00" 0 0 0 0 0 17 0 "" "0.0"
|
||
|
"{WK_TB00000004_TEMPLATES}" "TOOLBAR 0" 59419 1 0 "0.00" 0 0 0 0 0 17 0 "" "0.0"
|
||
|
"{WK_TB00000005_SEARCH}" "TOOLBAR 0" 59419 0 1 "0.00" 0 0 0 0 0 18 0 "" "0.0"
|
||
|
"{WK_TB00000007_DEBUG}" "TOOLBAR 0" 59419 2 0 "0.00" 0 0 0 0 0 17 0 "" "0.0"
|
||
|
"{WK_TB00000008_DEBUGRUN}" "TOOLBAR 0" 59419 2 1 "0.00" 0 0 0 0 0 17 0 "" "0.0"
|
||
|
"{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 1 3 "0.00" 0 0 0 0 0 17 0 "" "0.0"
|
||
|
"{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 1 4 "0.00" 0 0 0 0 0 17 0 "" "0.0"
|
||
|
"{WK_TB00000018_DEFAULTWINDOW}" "TOOLBAR 0" 59419 1 2 "0.00" 0 0 0 0 0 17 0 "" "0.0"
|
||
|
"{WK_TB00000026_MACRO}" "TOOLBAR 0" 59419 1 6 "0.00" 0 0 0 0 0 17 0 "" "0.0"
|
||
|
"{WK_TB00000028_RTOSDEBUG}" "TOOLBAR 0" 59419 2 2 "0.00" 0 0 0 0 0 17 0 "" "0.0"
|
||
|
"{WK_TB00000029_SYSTEMTOOL}" "TOOLBAR 0" 59419 2 3 "0.00" 0 0 0 0 0 17 0 "" "0.0"
|
||
|
[WINDOW_POSITION_STATE_DATA_VD2]
|
||
|
[WINDOW_POSITION_STATE_DATA_VD3]
|
||
|
[WINDOW_POSITION_STATE_DATA_VD4]
|
||
|
[WINDOW_Z_ORDER]
|
||
|
"D:\TP_sp4_CLAUD\sp4b3\SP4b3\SP4b3.c"
|
||
|
[TARGET_NAME]
|
||
|
"" "" 1769234797
|
||
|
[STATUSBAR_STATEINFO_VD1]
|
||
|
"MasterShowState" 1
|
||
|
"ApplicationShowState" 1
|
||
|
"DebuggerShowState" 1
|
||
|
[STATUSBAR_STATEINFO_VD2]
|
||
|
"MasterShowState" 1
|
||
|
"ApplicationShowState" 1
|
||
|
"DebuggerShowState" 1
|
||
|
[STATUSBAR_STATEINFO_VD3]
|
||
|
"MasterShowState" 1
|
||
|
"ApplicationShowState" 1
|
||
|
"DebuggerShowState" 1
|
||
|
[STATUSBAR_STATEINFO_VD4]
|
||
|
"MasterShowState" 1
|
||
|
"ApplicationShowState" 1
|
||
|
"DebuggerShowState" 1
|
||
|
[STATUSBAR_DEBUGGER_PANESTATE_VD1]
|
||
|
[STATUSBAR_DEBUGGER_PANESTATE_VD2]
|
||
|
[STATUSBAR_DEBUGGER_PANESTATE_VD3]
|
||
|
[STATUSBAR_DEBUGGER_PANESTATE_VD4]
|
||
|
[DEBUGGER_OPTIONS]
|
||
|
""
|
||
|
[DOWNLOAD_MODULES]
|
||
|
[CONNECT_ON_GO]
|
||
|
"FALSE"
|
||
|
[DOWNLOAD_MODULES_AFTER_BUILD]
|
||
|
"TRUE"
|
||
|
[REMOVE_BREAKPOINTS_ON_DOWNLOAD]
|
||
|
"FALSE"
|
||
|
[DISABLE_MEMORY_ACCESS_PRIOR_TO_COMMAND_FILE_EXECUTION]
|
||
|
"FALSE"
|
||
|
[LIMIT_DISASSEMBLY_MEMORY_ACCESS]
|
||
|
"FALSE"
|
||
|
[DISABLE_MEMORY_ACCESS_DURING_EXECUTION]
|
||
|
"FALSE"
|
||
|
[DEBUGGER_OPTIONS_PROPERTIES]
|
||
|
"1"
|
||
|
[COMMAND_FILES]
|
||
|
[DEFAULT_DEBUG_FORMAT]
|
||
|
""
|
||
|
[FLASH_DETAILS]
|
||
|
"" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" ""
|
||
|
[BREAKPOINTS]
|
||
|
[END]
|
||
| branch/CLAUD/sp4b3/SP4b3/SessionM32C_E8a_SYSTEM.ini | ||
|---|---|---|
|
[EMULATOR_SETTING]
|
||
|
HIDE_DIALOG=0
|
||
|
[RESET_RELEASE]
|
||
|
ENABLE=0
|
||
|
[CPU_SELECT]
|
||
|
DEVICE=M30879FL
|
||
|
EMUSEL=0
|
||
|
MCU_GROUP=M32C__87 Group
|
||
|
[POWER_SUPPLY]
|
||
|
VOLTAGE_5_0=0
|
||
|
VOLTAGE_3_3=0
|
||
|
[FW_LOCATE]
|
||
|
FWADDRESS=fff0
|
||
|
RAMADDRESS=c3
|
||
|
[WDT]
|
||
|
WDT_USE=0
|
||
|
[MCU_SETTING]
|
||
|
PROCESSOR_MODE=0
|
||
|
[COMMUNI]
|
||
|
COMSPEED=8
|
||
|
[Driver Configuration]
|
||
|
Renesas Communications=USB interface,0,
|
||
|
[Target]
|
||
|
M32C E8a SYSTEM=Renesas Communications
|
||
| branch/CLAUD/sp4b3/SP4b3/sfr32c87.h | ||
|---|---|---|
|
/************************************************************************************
|
||
|
* *
|
||
|
* File name : sfr32c87.h *
|
||
|
* Contents : Definition of M32C/87 Group SFR *
|
||
|
* *
|
||
|
* Copyright, 2003 RENESAS TECHNOLOGY CORPORATION *
|
||
|
* AND RENESAS SOLUTIONS CORPORATION *
|
||
|
* *
|
||
|
* Note : *
|
||
|
* *
|
||
|
* Version : Ver 0.01 (04-09-23) Preliminary *
|
||
|
* These data made based on M32C/85 Group H/W Manual Rev.0.30 *
|
||
|
* Version : Ver 0.02 (04-12-02) Preliminary *
|
||
|
* Version : Ver 0.03 (04-12-22) Preliminary *
|
||
|
* Version : Ver 0.04 (05-12-08) Preliminary *
|
||
|
* Version : Ver 0.05 (06-01-23) Preliminary *
|
||
|
* *
|
||
|
*************************************************************************************/
|
||
|
/*
|
||
|
note:
|
||
|
This data is a freeware that SFR for M32C/87 group are described.
|
||
|
RENESAS TECHNOLOGY CORPORATION and RENESAS SOLUTIONS CORPORATION assume
|
||
|
no responsibility for any damage that occurred by this data.
|
||
|
*/
|
||
|
|
||
|
/************************************************************************
|
||
|
* declare SFR address *
|
||
|
************************************************************************/
|
||
|
#pragma ADDRESS pm0_addr 0004H /* Processor mode register 0 */
|
||
|
#pragma ADDRESS pm1_addr 0005H /* Processor mode register 1 */
|
||
|
#pragma ADDRESS cm0_addr 0006H /* System clock control register 0 */
|
||
|
#pragma ADDRESS cm1_addr 0007H /* System clock control register 1 */
|
||
|
|
||
|
#pragma ADDRESS aier_addr 0009H /* Address match interrupt enable register */
|
||
|
#pragma ADDRESS prcr_addr 000aH /* Protect register */
|
||
|
#pragma ADDRESS ds_addr 000bH /* External data bus width control register */
|
||
|
#pragma ADDRESS mcd_addr 000cH /* Main clock division register */
|
||
|
#pragma ADDRESS cm2_addr 000dH /* Oscillation stop detect register */
|
||
|
#pragma ADDRESS wdts_addr 000eH /* Watchdog timer start register */
|
||
|
#pragma ADDRESS wdc_addr 000fH /* Watchdog timer control register */
|
||
|
#pragma ADDRESS rmad0_addr 0010H /* Address match interrupt register 0 */
|
||
|
#pragma ADDRESS pm2_addr 0013H /* Processor mode register 2 */
|
||
|
#pragma ADDRESS rmad1_addr 0014H /* Address match interrupt register 1 */
|
||
|
#pragma ADDRESS vcr2_addr 0017H /* Voltage detection register 2 */
|
||
|
#pragma ADDRESS rmad2_addr 0018H /* Address match interrupt register 2 */
|
||
|
#pragma ADDRESS vcr1_addr 001bH /* Voltage detection register 1 */
|
||
|
#pragma ADDRESS rmad3_addr 001cH /* Address match interrupt register 3 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS plc_addr 0026H /* PLL control register */
|
||
|
#pragma ADDRESS plc0_addr 0026H /* PLL control register 0 */
|
||
|
#pragma ADDRESS plc1_addr 0027H /* PLL control register 1 */
|
||
|
#pragma ADDRESS rmad4_addr 0028H /* Address match interrupt register 4 */
|
||
|
|
||
|
#pragma ADDRESS rmad5_addr 002CH /* Address match interrupt register 5 */
|
||
|
#pragma ADDRESS d4int_addr 002FH /* Voltage down detect interrupt register */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS rmad6_addr 0038H /* Address match interrupt register 6 */
|
||
|
#pragma ADDRESS rmad7_addr 003CH /* Address match interrupt register 7 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS ewcr0_addr 0048H /* External space wait control register 0 */
|
||
|
#pragma ADDRESS ewcr1_addr 0049H /* External space wait control register 1 */
|
||
|
#pragma ADDRESS ewcr2_addr 004AH /* External space wait control register 2 */
|
||
|
#pragma ADDRESS ewcr3_addr 004BH /* External space wait control register 3 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS fmr1_addr 0055H /* Flash Memory Control Register 1 */
|
||
|
|
||
|
#pragma ADDRESS fmr_addr 0057H /* Flash memory control register 0 */
|
||
|
#pragma ADDRESS fmr0_addr 0057H /* Flash memory control register 0 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS dm0ic_addr 0068H /* DMA0 interrupt control register */
|
||
|
#pragma ADDRESS tb5ic_addr 0069H /* Timer B5 interrupt register */
|
||
|
#pragma ADDRESS dm2ic_addr 006aH /* DMA2 interrupt register */
|
||
|
#pragma ADDRESS s2ric_addr 006bH /* UART2 receive/ack interrupt control register */
|
||
|
#pragma ADDRESS ta0ic_addr 006cH /* Timer A0 interrupt control register */
|
||
|
#pragma ADDRESS s3ric_addr 006dH /* UART3 receive/ack interrupt control register */
|
||
|
#pragma ADDRESS ta2ic_addr 006eH /* Timer A2 interrupt control register */
|
||
|
#pragma ADDRESS s4ric_addr 006fH /* UART4 receive/ack interrupt control register */
|
||
|
#pragma ADDRESS ta4ic_addr 0070H /* Timer A4 interrupt control register */
|
||
|
#pragma ADDRESS bcn0ic_addr 0071H /* Bus collision (UART0) interrupt control register */
|
||
|
#pragma ADDRESS bcn3ic_addr 0071H /* Bus collision (UART3) interrupt control register */
|
||
|
#pragma ADDRESS s0ric_addr 0072H /* UART0 receive interrupt control register */
|
||
|
#pragma ADDRESS ad0ic_addr 0073H /* A/D0 conversion interrupt control register */
|
||
|
#pragma ADDRESS s1ric_addr 0074H /* UART1 receive interrupt control register */
|
||
|
#pragma ADDRESS iio0ic_addr 0075H /* Intelligent I/O interrupt control register 0 */
|
||
|
#pragma ADDRESS can3ic_addr 0075H /* CAN interrupt 3 control register */
|
||
|
#pragma ADDRESS tb1ic_addr 0076H /* Timer B1 interrupt control register */
|
||
|
#pragma ADDRESS iio2ic_addr 0077H /* Intelligent I/O interrupt control register 2 */
|
||
|
#pragma ADDRESS tb3ic_addr 0078H /* Timer B3 interrupt control register */
|
||
|
#pragma ADDRESS iio4ic_addr 0079H /* Intelligent I/O interrupt control register 4 */
|
||
|
#pragma ADDRESS int5ic_addr 007aH /* INT5~ interrupt control register */
|
||
|
#pragma ADDRESS iio6ic_addr 007bH /* Intelligent I/O interrupt control register 6 */
|
||
|
#pragma ADDRESS int3ic_addr 007cH /* INT3~ interrupt control register */
|
||
|
#pragma ADDRESS iio8ic_addr 007dH /* Intelligent I/O interrupt control register 8 */
|
||
|
#pragma ADDRESS int1ic_addr 007eH /* INT1~ interrupt control register */
|
||
|
#pragma ADDRESS iio10ic_addr 007fH /* Intelligent I/O interrupt control register 10 */
|
||
|
#pragma ADDRESS can1ic_addr 007fH /* CAN Interrupt 1 Control Register */
|
||
|
|
||
|
#pragma ADDRESS iio11ic_addr 0081H /* Intelligent I/O interrupt control register 11 */
|
||
|
#pragma ADDRESS can2ic_addr 0081H /* CAN Interrupt 2 Control Register */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS dm1ic_addr 0088H /* DMA1 interrupt control register */
|
||
|
#pragma ADDRESS s2tic_addr 0089H /* UART2 transmit/nack interrupt control register */
|
||
|
#pragma ADDRESS dm3ic_addr 008aH /* DMA3 interrupt control register */
|
||
|
#pragma ADDRESS s3tic_addr 008bH /* UART3 transmit/nack interrupt control register */
|
||
|
#pragma ADDRESS ta1ic_addr 008cH /* Timer A1 interrupt control register */
|
||
|
#pragma ADDRESS s4tic_addr 008dH /* UART4 transmit/nack interrupt control register */
|
||
|
#pragma ADDRESS ta3ic_addr 008eH /* Timer A3 interrupt control register */
|
||
|
#pragma ADDRESS bcn2ic_addr 008fH /* Bus collision (UART2) interrupt control register */
|
||
|
#pragma ADDRESS s0tic_addr 0090H /* UART0 transmit interrupt control register */
|
||
|
#pragma ADDRESS bcn1ic_addr 0091H /* Bus collision (UART1) interrupt control register*/
|
||
|
#pragma ADDRESS bcn4ic_addr 0091H /* Bus collision (UART4) interrupt control register */
|
||
|
#pragma ADDRESS s1tic_addr 0092H /* UART1 transmit interrupt control register */
|
||
|
#pragma ADDRESS kupic_addr 0093H /* Key input interrupt control register */
|
||
|
#pragma ADDRESS tb0ic_addr 0094H /* Timer B0 interrupt control register */
|
||
|
#pragma ADDRESS iio1ic_addr 0095H /* Intelligent I/O interrupt control register 1 */
|
||
|
#pragma ADDRESS can4ic_addr 0095H /* CAN Interrupt 4 Control Register */
|
||
|
#pragma ADDRESS tb2ic_addr 0096H /* Timer B2 interrupt control register */
|
||
|
#pragma ADDRESS iio3ic_addr 0097H /* Intelligent I/O interrupt control register 3 */
|
||
|
#pragma ADDRESS tb4ic_addr 0098H /* Timer B4 interrupt control register */
|
||
|
#pragma ADDRESS iio5ic_addr 0099H /* Intelligent I/O interrupt control register 5 */
|
||
|
#pragma ADDRESS can5ic_addr 0099H /* CAN Interrupt 5 Control Register */
|
||
|
#pragma ADDRESS int4ic_addr 009aH /* INT4~ interrupt control register */
|
||
|
#pragma ADDRESS iio7ic_addr 009bH /* Intelligent I/O interrupt control register 7 */
|
||
|
#pragma ADDRESS int2ic_addr 009cH /* INT2~ interrupt control register */
|
||
|
#pragma ADDRESS iio9ic_addr 009dH /* Intelligent I/O interrupt control register 9 */
|
||
|
#pragma ADDRESS can0ic_addr 009dH /* CAN0 Interrupt Control Register*/
|
||
|
#pragma ADDRESS int0ic_addr 009eH /* INT0~ interrupt control register */
|
||
|
#pragma ADDRESS rlvl_addr 009fH /* Exit priority register */
|
||
|
#pragma ADDRESS iio0ir_addr 00a0H /* Interrupt request register 0 */
|
||
|
#pragma ADDRESS iio1ir_addr 00a1H /* Interrupt request register 1 */
|
||
|
#pragma ADDRESS iio2ir_addr 00a2H /* Interrupt request register 2 */
|
||
|
#pragma ADDRESS iio3ir_addr 00a3H /* Interrupt request register 3 */
|
||
|
#pragma ADDRESS iio4ir_addr 00a4H /* Interrupt request register 4 */
|
||
|
#pragma ADDRESS iio5ir_addr 00a5H /* Interrupt request register 5 */
|
||
|
#pragma ADDRESS iio6ir_addr 00a6H /* Interrupt request register 6 */
|
||
|
#pragma ADDRESS iio7ir_addr 00a7H /* Interrupt request register 7 */
|
||
|
#pragma ADDRESS iio8ir_addr 00a8H /* Interrupt request register 8 */
|
||
|
#pragma ADDRESS iio9ir_addr 00a9H /* Interrupt request register 9 */
|
||
|
#pragma ADDRESS iio10ir_addr 00aaH /* Interrupt request register 10 */
|
||
|
#pragma ADDRESS iio11ir_addr 00abH /* Interrupt request register 11 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS iio0ie_addr 00b0H /* Interrupt enable register 0 */
|
||
|
#pragma ADDRESS iio1ie_addr 00b1H /* Interrupt enable register 1 */
|
||
|
#pragma ADDRESS iio2ie_addr 00b2H /* Interrupt enable register 2 */
|
||
|
#pragma ADDRESS iio3ie_addr 00b3H /* Interrupt enable register 3 */
|
||
|
#pragma ADDRESS iio4ie_addr 00b4H /* Interrupt enable register 4 */
|
||
|
#pragma ADDRESS iio5ie_addr 00b5H /* Interrupt enable register 5 */
|
||
|
#pragma ADDRESS iio6ie_addr 00b6H /* Interrupt enable register 6 */
|
||
|
#pragma ADDRESS iio7ie_addr 00b7H /* Interrupt enable register 7 */
|
||
|
#pragma ADDRESS iio8ie_addr 00b8H /* Interrupt enable register 8 */
|
||
|
#pragma ADDRESS iio9ie_addr 00b9H /* Interrupt enable register 9 */
|
||
|
#pragma ADDRESS iio10ie_addr 00baH /* Interrupt enable register 10 */
|
||
|
#pragma ADDRESS iio11ie_addr 00bbH /* Interrupt enable register 11 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS g0rb_addr 00e8H /* SI/O receive buffer register 0 */
|
||
|
#pragma ADDRESS g0tb_addr 00eaH /* Transmit buffer register 0 */
|
||
|
#pragma ADDRESS g0dr_addr 00eaH /* Receive data register 0 */
|
||
|
|
||
|
#pragma ADDRESS g0ri_addr 00ecH /* Receive input register 0 */
|
||
|
#pragma ADDRESS g0mr_addr 00edH /* SI/O communication control register 0 */
|
||
|
#pragma ADDRESS g0to_addr 00eeH /* Transmit output register 0 */
|
||
|
#pragma ADDRESS g0cr_addr 00efH /* SI/O communication control register 0 */
|
||
|
#pragma ADDRESS g0cmp0_addr 00f0H /* Data compare register 00 */
|
||
|
#pragma ADDRESS g0cmp1_addr 00f1H /* Data compare register 01 */
|
||
|
#pragma ADDRESS g0cmp2_addr 00f2H /* Data compare register 02 */
|
||
|
#pragma ADDRESS g0cmp3_addr 00f3H /* Data compare register 03 */
|
||
|
#pragma ADDRESS g0msk0_addr 00f4H /* Data mask register 00 */
|
||
|
#pragma ADDRESS g0msk1_addr 00f5H /* Data mask register 01 */
|
||
|
#pragma ADDRESS ccs_addr 00f6H /* Communication clock select register */
|
||
|
|
||
|
#pragma ADDRESS g0rcrc_addr 00f8H /* Receive CRC code register 0 */
|
||
|
#pragma ADDRESS g0tcrc_addr 00faH /* Transmit CRC code register 0 */
|
||
|
#pragma ADDRESS g0emr_addr 00fcH /* SI/O expansion mode register 0 */
|
||
|
#pragma ADDRESS g0erc_addr 00fdH /* SI/O expansion receive control register 0 */
|
||
|
#pragma ADDRESS g0irf_addr 00feH /* SI/O special communication interrupt detect register 0 */
|
||
|
#pragma ADDRESS g0etc_addr 00ffH /* SI/O expansion transmit control register 0 */
|
||
|
#pragma ADDRESS g1tm0_addr 0100H /* Time measurement register 10 */
|
||
|
#pragma ADDRESS g1po0_addr 0100H /* Waveform generate register 10 */
|
||
|
#pragma ADDRESS g1tm1_addr 0102H /* Time measurement register 11 */
|
||
|
#pragma ADDRESS g1po1_addr 0102H /* Waveform generate register 11 */
|
||
|
#pragma ADDRESS g1tm2_addr 0104H /* Time measurement register 12 */
|
||
|
#pragma ADDRESS g1po2_addr 0104H /* Waveform generate register 12 */
|
||
|
#pragma ADDRESS g1tm3_addr 0106H /* Time measurement register 13 */
|
||
|
#pragma ADDRESS g1po3_addr 0106H /* Waveform generate register 13 */
|
||
|
#pragma ADDRESS g1tm4_addr 0108H /* Time measurement register 14 */
|
||
|
#pragma ADDRESS g1po4_addr 0108H /* Waveform generate register 14 */
|
||
|
#pragma ADDRESS g1tm5_addr 010aH /* Time measurement register 15 */
|
||
|
#pragma ADDRESS g1po5_addr 010aH /* Waveform generate register 15 */
|
||
|
#pragma ADDRESS g1tm6_addr 010cH /* Time measurement register 16 */
|
||
|
#pragma ADDRESS g1po6_addr 010cH /* Waveform generate register 16 */
|
||
|
#pragma ADDRESS g1tm7_addr 010eH /* Time measurement register 17 */
|
||
|
#pragma ADDRESS g1po7_addr 010eH /* Waveform generate register 17 */
|
||
|
#pragma ADDRESS g1pocr0_addr 0110H /* Waveform generate control register 10 */
|
||
|
#pragma ADDRESS g1pocr1_addr 0111H /* Waveform generate control register 11 */
|
||
|
#pragma ADDRESS g1pocr2_addr 0112H /* Waveform generate control register 12 */
|
||
|
#pragma ADDRESS g1pocr3_addr 0113H /* Waveform generate control register 13 */
|
||
|
#pragma ADDRESS g1pocr4_addr 0114H /* Waveform generate control register 14 */
|
||
|
#pragma ADDRESS g1pocr5_addr 0115H /* Waveform generate control register 15 */
|
||
|
#pragma ADDRESS g1pocr6_addr 0116H /* Waveform generate control register 16 */
|
||
|
#pragma ADDRESS g1pocr7_addr 0117H /* Waveform generate control register 17 */
|
||
|
#pragma ADDRESS g1tmcr0_addr 0118H /* Time measurement control register 10 */
|
||
|
#pragma ADDRESS g1tmcr1_addr 0119H /* Time measurement control register 11 */
|
||
|
#pragma ADDRESS g1tmcr2_addr 011aH /* Time measurement control register 12 */
|
||
|
#pragma ADDRESS g1tmcr3_addr 011bH /* Time measurement control register 13 */
|
||
|
#pragma ADDRESS g1tmcr4_addr 011cH /* Time measurement control register 14 */
|
||
|
#pragma ADDRESS g1tmcr5_addr 011dH /* Time measurement control register 15 */
|
||
|
#pragma ADDRESS g1tmcr6_addr 011eH /* Time measurement control register 16 */
|
||
|
#pragma ADDRESS g1tmcr7_addr 011fH /* Time measurement control register 17 */
|
||
|
#pragma ADDRESS g1bt_addr 0120H /* Base timer register 1 */
|
||
|
#pragma ADDRESS g1bcr0_addr 0122H /* Base timer control register 10 */
|
||
|
#pragma ADDRESS g1bcr1_addr 0123H /* Base timer control register 11 */
|
||
|
#pragma ADDRESS g1tpr6_addr 0124H /* Time measurement prescaler register 16 */
|
||
|
#pragma ADDRESS g1tpr7_addr 0125H /* Time measurement prescaler register 17 */
|
||
|
#pragma ADDRESS g1fe_addr 0126H /* Function enable register 1 */
|
||
|
#pragma ADDRESS g1fs_addr 0127H /* Function select register 1 */
|
||
|
#pragma ADDRESS g1rb_addr 0128H /* SI/O receive buffer register 1 */
|
||
|
#pragma ADDRESS g1tb_addr 012aH /* Transmit buffer register 1 */
|
||
|
#pragma ADDRESS g1dr_addr 012aH /* Receive data register 1 */
|
||
|
|
||
|
#pragma ADDRESS g1ri_addr 012cH /* Receive input register 1 */
|
||
|
#pragma ADDRESS g1mr_addr 012dH /* SI/O communication mode register 1 */
|
||
|
#pragma ADDRESS g1to_addr 012eH /* Transmit output register 1 */
|
||
|
#pragma ADDRESS g1cr_addr 012fH /* SI/O communication control register 1 */
|
||
|
#pragma ADDRESS g1cmp0_addr 0130H /* Data compare register 10 */
|
||
|
#pragma ADDRESS g1cmp1_addr 0131H /* Data compare register 11 */
|
||
|
#pragma ADDRESS g1cmp2_addr 0132H /* Data compare register 12 */
|
||
|
#pragma ADDRESS g1cmp3_addr 0133H /* Data compare register 13 */
|
||
|
#pragma ADDRESS g1msk0_addr 0134H /* Data mask register 10 */
|
||
|
#pragma ADDRESS g1msk1_addr 0135H /* Data mask register 11 */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS g1rcrc_addr 0138H /* Receive CRC code register 1 */
|
||
|
#pragma ADDRESS g1tcrc_addr 013aH /* Transmit CRC code register 1 */
|
||
|
#pragma ADDRESS g1emr_addr 013cH /* SI/O extended mode register 1 */
|
||
|
#pragma ADDRESS g1erc_addr 013dH /* SI/O extended receive control register 1 */
|
||
|
#pragma ADDRESS g1irf_addr 013eH /* SI/O special communication interrupt detect register 1 */
|
||
|
#pragma ADDRESS g1etc_addr 013fH /* SI/O extended transmit control register 1 */
|
||
|
|
||
|
#pragma ADDRESS g2po0_addr 0140H
|
||
|
#pragma ADDRESS g2po1_addr 0142H
|
||
|
#pragma ADDRESS g2po2_addr 0144H
|
||
|
#pragma ADDRESS g2po3_addr 0146H
|
||
|
#pragma ADDRESS g2po4_addr 0148H
|
||
|
#pragma ADDRESS g2po5_addr 014aH
|
||
|
#pragma ADDRESS g2po6_addr 014cH
|
||
|
#pragma ADDRESS g2po7_addr 014eH
|
||
|
#pragma ADDRESS g2pocr0_addr 0150H
|
||
|
#pragma ADDRESS g2pocr1_addr 0151H
|
||
|
#pragma ADDRESS g2pocr2_addr 0152H
|
||
|
#pragma ADDRESS g2pocr3_addr 0153H
|
||
|
#pragma ADDRESS g2pocr4_addr 0154H
|
||
|
#pragma ADDRESS g2pocr5_addr 0155H
|
||
|
#pragma ADDRESS g2pocr6_addr 0156H
|
||
|
#pragma ADDRESS g2pocr7_addr 0157H
|
||
|
|
||
|
|
||
|
#pragma ADDRESS g2bt_addr 0160H
|
||
|
#pragma ADDRESS g2bcr0_addr 0162H
|
||
|
#pragma ADDRESS g2bcr1_addr 0163H
|
||
|
#pragma ADDRESS btsr_addr 0164H
|
||
|
|
||
|
#pragma ADDRESS g2fe_addr 0166H
|
||
|
#pragma ADDRESS g2rtp_addr 0167H
|
||
|
|
||
|
|
||
|
#pragma ADDRESS g2mr_addr 016aH
|
||
|
#pragma ADDRESS g2cr_addr 016bH
|
||
|
#pragma ADDRESS g2tb_addr 016cH
|
||
|
#pragma ADDRESS g2rb_addr 016eH
|
||
|
#pragma ADDRESS iear_addr 0170H
|
||
|
#pragma ADDRESS iecr_addr 0172H
|
||
|
#pragma ADDRESS ietif_addr 0173H
|
||
|
#pragma ADDRESS ierif_addr 0174H
|
||
|
|
||
|
|
||
|
#pragma ADDRESS ipsb_addr 0177H /* Input function select register B */
|
||
|
#pragma ADDRESS ips_addr 0178H /* Input function select register */
|
||
|
#pragma ADDRESS ipsa_addr 0179H /* Input function select register A */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS u5mr_addr 01c0H /* UART5 transmit/receive mode register */
|
||
|
#pragma ADDRESS u5brg_addr 01c1H /* UART5 bit rate generator */
|
||
|
#pragma ADDRESS u5tb_addr 01c2H /* UART5 transmit buffer register */
|
||
|
#pragma ADDRESS u5c0_addr 01c4H /* UART5 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u5c1_addr 01c5H /* UART5 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u5rb_addr 01c6H /* UART5 receive buffer register */
|
||
|
#pragma ADDRESS u6mr_addr 01c8H /* UART6 transmit/receive mode register */
|
||
|
#pragma ADDRESS u6brg_addr 01c9H /* UART6 bit rate generator */
|
||
|
#pragma ADDRESS u6tb_addr 01caH /* UART6 transmit buffer register */
|
||
|
#pragma ADDRESS u6c0_addr 01ccH /* UART6 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u6c1_addr 01cdH /* UART6 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u6rb_addr 01ceH /* UART6 receive buffer register */
|
||
|
#pragma ADDRESS u56con_addr 01d0H
|
||
|
#pragma ADDRESS u56is_addr 01d1H
|
||
|
|
||
|
|
||
|
#pragma ADDRESS rtp0r_addr 01d8H
|
||
|
#pragma ADDRESS rtp1r_addr 01d9H
|
||
|
#pragma ADDRESS rtp2r_addr 01daH
|
||
|
#pragma ADDRESS rtp3r_addr 01dbH
|
||
|
|
||
|
|
||
|
|
||
|
/************************************************************************
|
||
|
* CAN 0 SFR Address area *
|
||
|
************************************************************************/
|
||
|
#pragma ADDRESS c0slot 01e0H /* CAN0 Message Slot Buffer */
|
||
|
#pragma ADDRESS c0slot0 01e0H /* CAN0 Message Slot Buffer 0 */
|
||
|
#pragma ADDRESS c0slot1 01f0H /* CAN0 Message Slot Buffer 1 */
|
||
|
#pragma ADDRESS c0ctlr0_addr 0200H /* CAN0 Control Register 0 */
|
||
|
#pragma ADDRESS c0str_addr 0202H /* CAN0 Status Register */
|
||
|
#pragma ADDRESS c0idr_addr 0204H /* CAN0 Extended ID Register */
|
||
|
#pragma ADDRESS c0conr_addr 0206H /* CAN0 Configuration Register */
|
||
|
#pragma ADDRESS c0tsr_addr 0208H /* CAN0 Time Stamp Register */
|
||
|
#pragma ADDRESS c0tec_addr 020aH /* CAN0 Transmit Error Counter */
|
||
|
#pragma ADDRESS c0rec_addr 020bH /* CAN0 Receive Error Counter */
|
||
|
#pragma ADDRESS c0sistr_addr 020cH /* CAN0 Slot Interrupt Status Register */
|
||
|
#pragma ADDRESS c0simkr_addr 0210H /* CAN0 Slot Interrupt Mask Register */
|
||
|
#pragma ADDRESS c0eimkr_addr 0214H /* CAN0 Error Interrupt Mask Register */
|
||
|
#pragma ADDRESS c0eistr_addr 0215H /* CAN0 Error Interrupt Status Register */
|
||
|
#pragma ADDRESS c0efr_addr 0216H /* CAN0 Error Factor Register */
|
||
|
#pragma ADDRESS c0brp_addr 0217H /* CAN0 Baud Rate Prescaler */
|
||
|
#pragma ADDRESS c0mdr_addr 0219H /* CAN0 Mode Register */
|
||
|
#pragma ADDRESS c0ssctlr_addr 0220H /* (BANK0) CAN0 Single Shot Control Register */
|
||
|
#pragma ADDRESS c0ssstr_addr 0224H /* (BANK0) CAN0 Single Shot Status Register */
|
||
|
#pragma ADDRESS c0mctl 0230H /* (BANK0) CAN0 Message Control Register */
|
||
|
#pragma ADDRESS c0mctl0 0230H /* (BANK0) CAN0 Message Slot0 Control Register */
|
||
|
#pragma ADDRESS c0mctl1 0231H /* (BANK0) CAN0 Message Slot1 Control Register */
|
||
|
#pragma ADDRESS c0mctl2 0232H /* (BANK0) CAN0 Message Slot2 Control Register */
|
||
|
#pragma ADDRESS c0mctl3 0233H /* (BANK0) CAN0 Message Slot3 Control Register */
|
||
|
#pragma ADDRESS c0mctl4 0234H /* (BANK0) CAN0 Message Slot4 Control Register */
|
||
|
#pragma ADDRESS c0mctl5 0235H /* (BANK0) CAN0 Message Slot5 Control Register */
|
||
|
#pragma ADDRESS c0mctl6 0236H /* (BANK0) CAN0 Message Slot6 Control Register */
|
||
|
#pragma ADDRESS c0mctl7 0237H /* (BANK0) CAN0 Message Slot7 Control Register */
|
||
|
#pragma ADDRESS c0mctl8 0238H /* (BANK0) CAN0 Message Slot8 Control Register */
|
||
|
#pragma ADDRESS c0mctl9 0239H /* (BANK0) CAN0 Message Slot9 Control Register */
|
||
|
#pragma ADDRESS c0mctl10 023aH /* (BANK0) CAN0 Message Slot10 Control Register */
|
||
|
#pragma ADDRESS c0mctl11 023bH /* (BANK0) CAN0 Message Slot11 Control Register */
|
||
|
#pragma ADDRESS c0mctl12 023cH /* (BANK0) CAN0 Message Slot12 Control Register */
|
||
|
#pragma ADDRESS c0mctl13 023dH /* (BANK0) CAN0 Message Slot13 Control Register */
|
||
|
#pragma ADDRESS c0mctl14 023eH /* (BANK0) CAN0 Message Slot14 Control Register */
|
||
|
#pragma ADDRESS c0mctl15 023fH /* (BANK0) CAN0 Message Slot15 Control Register */
|
||
|
#pragma ADDRESS c0gmr 0228H /* (BANK1) CAN0 Global Mask Register */
|
||
|
#pragma ADDRESS c0gmr0_addr 0228H /* (BANK1) CAN0 Global Mask Register 0 */
|
||
|
#pragma ADDRESS c0gmr1_addr 0229H /* (BANK1) CAN0 Global Mask Register 1 */
|
||
|
#pragma ADDRESS c0gmr2_addr 022aH /* (BANK1) CAN0 Global Mask Register 2 */
|
||
|
#pragma ADDRESS c0gmr3_addr 022bH /* (BANK1) CAN0 Global Mask Register 3 */
|
||
|
#pragma ADDRESS c0gmr4_addr 022cH /* (BANK1) CAN0 Global Mask Register 4 */
|
||
|
#pragma ADDRESS c0lmar 0230H /* (BANK1) CAN0 Local Mask A Register */
|
||
|
#pragma ADDRESS c0lmar0_addr 0230H /* (BANK1) CAN0 Local Mask A Register 0 */
|
||
|
#pragma ADDRESS c0lmar1_addr 0231H /* (BANK1) CAN0 Local Mask A Register 1 */
|
||
|
#pragma ADDRESS c0lmar2_addr 0232H /* (BANK1) CAN0 Local Mask A Register 2 */
|
||
|
#pragma ADDRESS c0lmar3_addr 0233H /* (BANK1) CAN0 Local Mask A Register 3 */
|
||
|
#pragma ADDRESS c0lmar4_addr 0234H /* (BANK1) CAN0 Local Mask A Register 4 */
|
||
|
#pragma ADDRESS c0lmbr 0238H /* (BANK1) CAN0 Local Mask B Register */
|
||
|
#pragma ADDRESS c0lmbr0_addr 0238H /* (BANK1) CAN0 Local Mask B Register 0 */
|
||
|
#pragma ADDRESS c0lmbr1_addr 0239H /* (BANK1) CAN0 Local Mask B Register 1 */
|
||
|
#pragma ADDRESS c0lmbr2_addr 023aH /* (BANK1) CAN0 Local Mask B Register 2 */
|
||
|
#pragma ADDRESS c0lmbr3_addr 023bH /* (BANK1) CAN0 Local Mask B Register 3 */
|
||
|
#pragma ADDRESS c0lmbr4_addr 023cH /* (BANK1) CAN0 Local Mask B Register 4 */
|
||
|
#pragma ADDRESS c0sbs_addr 0240H /* CAN0 Slot Buffer Select Register */
|
||
|
#pragma ADDRESS c0ctlr1_addr 0241H /* CAN0 Control Register 1 */
|
||
|
#pragma ADDRESS c0slpr_addr 0242H /* CAN0 Sleep Control Register */
|
||
|
#pragma ADDRESS c0afs_addr 0244H /* CAN0 Acceptance Filter Support Register */
|
||
|
|
||
|
|
||
|
/************************************************************************
|
||
|
* CAN 1 SFR Address area *
|
||
|
************************************************************************/
|
||
|
#pragma ADDRESS c1slot 0260H /* CAN1 Message Slot Buffer */
|
||
|
#pragma ADDRESS c1slot0 0260H /* CAN1 Message Slot Buffer 0 */
|
||
|
#pragma ADDRESS c1slot1 0270H /* CAN1 Message Slot Buffer 1 */
|
||
|
#pragma ADDRESS c1ctlr0_addr 0280H /* CAN1 Control Register 0 */
|
||
|
#pragma ADDRESS c1str_addr 0282H /* CAN1 Status Register */
|
||
|
#pragma ADDRESS c1idr_addr 0284H /* CAN1 Extended ID Register */
|
||
|
#pragma ADDRESS c1conr_addr 0286H /* CAN1 Configuration Register */
|
||
|
#pragma ADDRESS c1tsr_addr 0288H /* CAN1 Time Stamp Register */
|
||
|
#pragma ADDRESS c1tec_addr 028aH /* CAN1 Transmit Error Counter */
|
||
|
#pragma ADDRESS c1rec_addr 028bH /* CAN1 Receive Error Counter */
|
||
|
#pragma ADDRESS c1sistr_addr 028cH /* CAN1 Slot Interrupt Status Register */
|
||
|
#pragma ADDRESS c1simkr_addr 0290H /* CAN1 Slot Interrupt Mask Register */
|
||
|
#pragma ADDRESS c1eimkr_addr 0294H /* CAN1 Error Interrupt Mask Register */
|
||
|
#pragma ADDRESS c1eistr_addr 0295H /* CAN1 Error Interrupt Status Register */
|
||
|
#pragma ADDRESS c1efr_addr 0296H /* CAN1 Error Factor Register */
|
||
|
#pragma ADDRESS c1brp_addr 0297H /* CAN1 Baud Rate Prescaler */
|
||
|
#pragma ADDRESS c1mdr_addr 0299H /* CAN1 Mode Register */
|
||
|
#pragma ADDRESS c1ssctlr_addr 02A0H /* (BANK0) CAN1 Single Shot Control Register */
|
||
|
#pragma ADDRESS c1ssstr_addr 02A4H /* (BANK0) CAN1 Single Shot Status Register */
|
||
|
#pragma ADDRESS c1mctl 02B0H /* (BANK0) CAN1 Message Control Register */
|
||
|
#pragma ADDRESS c1mctl0 02B0H /* (BANK0) CAN1 Message Slot0 Control Register */
|
||
|
#pragma ADDRESS c1mctl1 02B1H /* (BANK0) CAN1 Message Slot1 Control Register */
|
||
|
#pragma ADDRESS c1mctl2 02B2H /* (BANK0) CAN1 Message Slot2 Control Register */
|
||
|
#pragma ADDRESS c1mctl3 02B3H /* (BANK0) CAN1 Message Slot3 Control Register */
|
||
|
#pragma ADDRESS c1mctl4 02B4H /* (BANK0) CAN1 Message Slot4 Control Register */
|
||
|
#pragma ADDRESS c1mctl5 02B5H /* (BANK0) CAN1 Message Slot5 Control Register */
|
||
|
#pragma ADDRESS c1mctl6 02B6H /* (BANK0) CAN1 Message Slot6 Control Register */
|
||
|
#pragma ADDRESS c1mctl7 02B7H /* (BANK0) CAN1 Message Slot7 Control Register */
|
||
|
#pragma ADDRESS c1mctl8 02B8H /* (BANK0) CAN1 Message Slot8 Control Register */
|
||
|
#pragma ADDRESS c1mctl9 02B9H /* (BANK0) CAN1 Message Slot9 Control Register */
|
||
|
#pragma ADDRESS c1mctl10 02baH /* (BANK0) CAN1 Message Slot10 Control Register */
|
||
|
#pragma ADDRESS c1mctl11 02bbH /* (BANK0) CAN1 Message Slot11 Control Register */
|
||
|
#pragma ADDRESS c1mctl12 02bcH /* (BANK0) CAN1 Message Slot12 Control Register */
|
||
|
#pragma ADDRESS c1mctl13 02bdH /* (BANK0) CAN1 Message Slot13 Control Register */
|
||
|
#pragma ADDRESS c1mctl14 02beH /* (BANK0) CAN1 Message Slot14 Control Register */
|
||
|
#pragma ADDRESS c1mctl15 02bfH /* (BANK0) CAN1 Message Slot15 Control Register */
|
||
|
#pragma ADDRESS c1gmr 02a8H /* (BANK1) CAN1 Global Mask Register */
|
||
|
#pragma ADDRESS c1gmr0_addr 02a8H /* (BANK1) CAN1 Global Mask Register 0 */
|
||
|
#pragma ADDRESS c1gmr1_addr 02a9H /* (BANK1) CAN1 Global Mask Register 1 */
|
||
|
#pragma ADDRESS c1gmr2_addr 02aaH /* (BANK1) CAN1 Global Mask Register 2 */
|
||
|
#pragma ADDRESS c1gmr3_addr 02abH /* (BANK1) CAN1 Global Mask Register 3 */
|
||
|
#pragma ADDRESS c1gmr4_addr 02acH /* (BANK1) CAN1 Global Mask Register 4 */
|
||
|
#pragma ADDRESS c1lmar 02b0H /* (BANK1) CAN1 Local Mask A Register */
|
||
|
#pragma ADDRESS c1lmar0_addr 02b0H /* (BANK1) CAN1 Local Mask A Register 0 */
|
||
|
#pragma ADDRESS c1lmar1_addr 02b1H /* (BANK1) CAN1 Local Mask A Register 1 */
|
||
|
#pragma ADDRESS c1lmar2_addr 02b2H /* (BANK1) CAN1 Local Mask A Register 2 */
|
||
|
#pragma ADDRESS c1lmar3_addr 02b3H /* (BANK1) CAN1 Local Mask A Register 3 */
|
||
|
#pragma ADDRESS c1lmar4_addr 02b4H /* (BANK1) CAN1 Local Mask A Register 4 */
|
||
|
#pragma ADDRESS c1lmbr 02b8H /* (BANK1) CAN1 Local Mask B Register */
|
||
|
#pragma ADDRESS c1lmbr0_addr 02b8H /* (BANK1) CAN1 Local Mask B Register 0 */
|
||
|
#pragma ADDRESS c1lmbr1_addr 02b9H /* (BANK1) CAN1 Local Mask B Register 1 */
|
||
|
#pragma ADDRESS c1lmbr2_addr 02baH /* (BANK1) CAN1 Local Mask B Register 2 */
|
||
|
#pragma ADDRESS c1lmbr3_addr 02bbH /* (BANK1) CAN1 Local Mask B Register 3 */
|
||
|
#pragma ADDRESS c1lmbr4_addr 02bcH /* (BANK1) CAN1 Local Mask B Register 4 */
|
||
|
#pragma ADDRESS c1sbs_addr 0250H /* CAN1 Slot Buffer Select Register */
|
||
|
#pragma ADDRESS c1ctlr1_addr 0251H /* CAN1 Control Register 1 */
|
||
|
#pragma ADDRESS c1slpr_addr 0252H /* CAN1 Sleep Control Register */
|
||
|
#pragma ADDRESS c1afs_addr 0254H /* CAN1 Acceptance Filter Support Register */
|
||
|
|
||
|
/************************************************************************
|
||
|
* *
|
||
|
************************************************************************/
|
||
|
#pragma ADDRESS x0r_addr 02c0H /* X0 register */
|
||
|
#pragma ADDRESS y0r_addr 02c0H /* Y0 register */
|
||
|
#pragma ADDRESS x1r_addr 02c2H /* X1 register */
|
||
|
#pragma ADDRESS y1r_addr 02c2H /* Y1 register */
|
||
|
#pragma ADDRESS x2r_addr 02c4H /* X2 register */
|
||
|
#pragma ADDRESS y2r_addr 02c4H /* Y2 register */
|
||
|
#pragma ADDRESS x3r_addr 02c6H /* X3 register */
|
||
|
#pragma ADDRESS y3r_addr 02c6H /* Y3 register */
|
||
|
#pragma ADDRESS x4r_addr 02c8H /* X4 register */
|
||
|
#pragma ADDRESS y4r_addr 02c8H /* Y4 register */
|
||
|
#pragma ADDRESS x5r_addr 02caH /* X5 register */
|
||
|
#pragma ADDRESS y5r_addr 02caH /* Y5 register */
|
||
|
#pragma ADDRESS x6r_addr 02ccH /* X6 register */
|
||
|
#pragma ADDRESS y6r_addr 02ccH /* Y6 register */
|
||
|
#pragma ADDRESS x7r_addr 02ceH /* X7 register */
|
||
|
#pragma ADDRESS y7r_addr 02ceH /* Y7 register */
|
||
|
#pragma ADDRESS x8r_addr 02d0H /* X8 register */
|
||
|
#pragma ADDRESS y8r_addr 02d0H /* Y8 register */
|
||
|
#pragma ADDRESS x9r_addr 02d2H /* X9 register */
|
||
|
#pragma ADDRESS y9r_addr 02d2H /* Y9 register */
|
||
|
#pragma ADDRESS x10r_addr 02d4H /* X10 register */
|
||
|
#pragma ADDRESS y10r_addr 02d4H /* Y10 register */
|
||
|
#pragma ADDRESS x11r_addr 02d6H /* X11 register */
|
||
|
#pragma ADDRESS y11r_addr 02d6H /* Y11 register */
|
||
|
#pragma ADDRESS x12r_addr 02d8H /* X12 register */
|
||
|
#pragma ADDRESS y12r_addr 02d8H /* Y12 register */
|
||
|
#pragma ADDRESS x13r_addr 02daH /* X13 register */
|
||
|
#pragma ADDRESS y13r_addr 02daH /* Y13 register */
|
||
|
#pragma ADDRESS x14r_addr 02dcH /* X14 register */
|
||
|
#pragma ADDRESS y14r_addr 02dcH /* Y14 register */
|
||
|
#pragma ADDRESS x15r_addr 02deH /* X15 register */
|
||
|
#pragma ADDRESS y15r_addr 02deH /* Y15 register */
|
||
|
#pragma ADDRESS xyc_addr 02e0H /* X-Y control register */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS u1smr4_addr 02e4H /* UART1 special mode register 4 */
|
||
|
#pragma ADDRESS u1smr3_addr 02e5H /* UART1 special mode register 3 */
|
||
|
#pragma ADDRESS u1smr2_addr 02e6H /* UART1 special mode register 2 */
|
||
|
#pragma ADDRESS u1smr_addr 02e7H /* UART1 special mode register */
|
||
|
#pragma ADDRESS u1mr_addr 02e8H /* UART1 transmit/receive mode register */
|
||
|
#pragma ADDRESS u1brg_addr 02e9H /* UART1 bit rate generator */
|
||
|
#pragma ADDRESS u1tb_addr 02eaH /* UART1 transmit buffer register */
|
||
|
#pragma ADDRESS u1c0_addr 02ecH /* UART1 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u1c1_addr 02edH /* UART1 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u1rb_addr 02eeH /* UART1 receive buffer register */
|
||
|
|
||
|
|
||
|
#pragma ADDRESS u4smr4_addr 02f4H /* UART4 special mode register 4 */
|
||
|
#pragma ADDRESS u4smr3_addr 02f5H /* UART4 special mode register 3 */
|
||
|
#pragma ADDRESS u4smr2_addr 02f6H /* UART4 special mode register 2 */
|
||
|
#pragma ADDRESS u4smr_addr 02f7H /* UART4 special mode register */
|
||
|
#pragma ADDRESS u4mr_addr 02f8H /* UART4 transmit/receive mode register */
|
||
|
#pragma ADDRESS u4brg_addr 02f9H /* UART4 bit rate generator */
|
||
|
#pragma ADDRESS u4tb_addr 02faH /* UART4 transmit buffer register */
|
||
|
#pragma ADDRESS u4c0_addr 02fcH /* UART4 transmit/receive control register 0 */
|
||
|
#pragma ADDRESS u4c1_addr 02fdH /* UART4 transmit/receive control register 1 */
|
||
|
#pragma ADDRESS u4rb_addr 02feH /* UART4 receive buffer register */
|
||
|
|
||
Formats disponibles : Unified diff
Mise en place projet TP6