root/branch/best/sp4c12/SP4b1/SP4b1/SP4b1.c @ 761
| 735 | albest | /***********************************************************************/
|
|
/* */
|
|||
/* FILE :SP4b1.c */
|
|||
/* DATE :Wed, Jun 02, 2021 */
|
|||
/* DESCRIPTION :main program file. */
|
|||
/* CPU GROUP :87B */
|
|||
/* */
|
|||
/* This file is generated by Renesas Project Generator (Ver.4.18). */
|
|||
/* NOTE:THIS IS A TYPICAL EXAMPLE. */
|
|||
/***********************************************************************/
|
|||
#include "sfr32c87.h"
|
|||
| 750 | albest | ||
void uart0_init(void); // Initialisation du port s?rie
|
|||
void uart0_tx(char c); //Envoie d'un caract?re
|
|||
char uart0_rx(void); //Fonction d'attente et lecture d'un caract?re
|
|||
int rectrame(char * Buffer);
|
|||
| 756 | albest | char * Buff;
|
|
| 735 | albest | void main(void)
|
|
{
|
|||
| 750 | albest | uart0_init();
|
|
| 756 | albest | while(1){
|
|
uart0_tx(rectrame(Buff));
|
|||
}
|
|||
| 735 | albest | }
|
|
| 756 | albest | ||
| 750 | albest | ||
void uart0_init(void){
|
|||
| 756 | albest | u0mr = 0x05;
|
|
| 750 | albest | u0brg = 32;
|
|
u0c0 = 0x11;
|
|||
u0c1 = 0x05;
|
|||
| 756 | albest | pd6_0 = 0;
|
|
pd6_1 = 0;
|
|||
pd6_2 = 0;
|
|||
pd6_3 = 1; //On affecte seulement les bits que l'on a besoin pour le bon fonctionnement
|
|||
ps0_3 = 1;
|
|||
| 750 | albest | }
|
|
void uart0_tx(char c){
|
|||
while (ti_u0c1 != 1);
|
|||
u0tb = c;
|
|||
}
|
|||
char uart0_rx(void){
|
|||
while (ri_u0c1 != 1);
|
|||
return u0rb;
|
|||
}
|
|||
int rectrame(char * Buffer){
|
|||
int i = 0;
|
|||
| 756 | albest | char car_recu;
|
|
char checksum = '0';
|
|||
car_recu = uart0_rx();
|
|||
while (car_recu != '$'){
|
|||
i = 0;
|
|||
checksum = '0';
|
|||
| 750 | albest | }
|
|
| 756 | albest | while (car_recu != '*'){
|
|
Buffer[i++] = car_recu;
|
|||
checksum = checksum ^ car_recu; // ^ est le ou exclusif
|
|||
}
|
|||
return i;
|
|||
| 750 | albest | }
|