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/***********************************************************************/
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/* */
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/* FILE :sp4c1.c */
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/* DATE :Thu, Jun 03, 2021 */
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/* DESCRIPTION :main program file. */
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/* CPU GROUP :87B */
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/* */
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/* This file is generated by Renesas Project Generator (Ver.4.18). */
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/* NOTE:THIS IS A TYPICAL EXAMPLE. */
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/***********************************************************************/
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#include "sfr32c87.h"
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void uart0_init(void);
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void uart0_tx(char c);
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char uart0_rx(void);
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void main(void)
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{
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uart0_init();
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while(1){
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uart0_tx('b');
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}
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}
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void uart0_init(void){
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pd6_1=0;
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ps6_2=0;
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ps0_3=1;
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ps0_2=0;
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ps0_2=0;
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//registre u0mr
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smd0_u0mr=1;//mode horloge synchrone
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smd1_u0mr=0;//mode UART 8-bits
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smd2_u0mr=1;//mode UART 8-bits
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ckdir_u0mr=0;//configuration horloge interne
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stps_u0mr=0;//configuration pour 2 bits de stops
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pry_u0mr=0;// selection du bit de parite
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prye_u0mr=0;//activation du bit de parite
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iopol_u0mr=0;//polarite non-inversee
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u0smr=0x00;
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u0smr2=0x00;
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u0smr3=0x00;
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u0smr4=0x00;
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//registre u0c0
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clk0_u0c0=1;/*configuration pour f8 */
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clk0_u0c0=0;
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crs_u0c0=1;//activation du clear to send (CTS)
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crd_u0c0=1;//
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nch_u0c0=0;//Selection Port de sortie : CMOS
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ckpol_u0c0=0;//
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uform_u0c0=0;//selection du LSB en premier
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//baud rate
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u0brg=0x20;//Initialisation du registre U0BRG a 32 bits
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//registre u0c1
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te_u0c1=0;//desactvation de la transmition d'operation
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re_u0c1=0;//desactvation de la reception d'operation
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u0lch_u0c1=0;
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u0rrm_u0c1=0;
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sclkstpb_u0c1=0;
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u0c1=0x05;
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}
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void uart0_tx(char c){
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crd_u0c0=1;
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crs_u0c0=0;
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te_u0c1=1;
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u0tb=c;
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te_u0c1=0;
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}
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