root/branch/FRAISSE/sp4c12/SP4c12/SP4c12.c @ 786
| 769 | lefraisse | /***********************************************************************/
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/* */
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/* FILE :SP4c12.c */
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/* DATE :Thu, Jun 03, 2021 */
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/* DESCRIPTION :main program file. */
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/* CPU GROUP :87B */
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/* */
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/* This file is generated by Renesas Project Generator (Ver.4.18). */
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/* NOTE:THIS IS A TYPICAL EXAMPLE. */
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/***********************************************************************/
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| 786 | lefraisse | #include "sfr32c87.h"
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| 769 | lefraisse | ||
| 786 | lefraisse | void uart0_init(void);
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void uart0_tx(char c);
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char uart0_rx(void);
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| 769 | lefraisse | void main(void)
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{
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| 786 | lefraisse | uart0_init();
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while(1){
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uart0_tx('o');
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//uart0_rx();
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}
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}
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void uart0_init(void){
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pd6_1=0;
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pd6_2=0;
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ps0_1=0;
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ps0_2=0;
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ps0_3=1;
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u0mr=0x05;
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| 769 | lefraisse | ||
| 786 | lefraisse | //Initialisaton du Registre U0SMR
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u0smr = 0x00;
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u0smr2 = 0x00;
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u0smr3 = 0x00;
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u0smr4 = 0x00;
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//Initialisaton du Registre U0C0
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clk1_u0c0 = 0;
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clk0_u0c0 = 1;
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crs_u0c0 = 1;
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crd_u0c0 = 1;
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nch_u0c0 = 0;
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ckpol_u0c0 = 0;
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uform_u0c0 = 0;
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//Initialisaton du Registre U0BRG
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u0brg = 0x20;
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//Initialisaton du Registre U0C1
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te_u0c1 = 0;
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re_u0c1 = 0;
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//uoirs_u0c1 = 0;
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u0rrm_u0c1 = 0;
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u0lch_u0c1 = 0;
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sclkstpb_u0c1 = 0;
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//Initialisaton du Registre S0TIC
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ilvl0_s0tic = 0;
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ilvl1_s0tic = 0;
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ilvl2_s0tic = 0;
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ir_s0tic = 0;
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//Initialisaton du Registre S0RIC
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ilvl0_s0ric = 0;
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ilvl1_s0ric = 0;
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ilvl2_s0ric = 0;
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ir_s0ric = 0;
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| 769 | lefraisse | }
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| 786 | lefraisse | ||
void uart0_tx(char c){
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//Bits TE et RE ? 1 (condition pour la transmission et la r?ception)
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te_u0c1=1;
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crd_u0c0=1;
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crs_u0c0=0;
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u0tb=c;
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te_u0c1=0;
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}
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//void uart0_rx((void){
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//while (u0c1_ri=0){
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// return u0rb;
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//}
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//}
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