Révision 203
Ajouté par Jacques LAFFONT il y a plus de 14 ans
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| trunk/librairies/polytech_ge/pont_diode/sym_2/master.tag | ||
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symbol.css
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| trunk/librairies/polytech_ge/pont_diode/sym_2/symbol.css | ||
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| trunk/librairies/polytech_ge/pont_diode/entity/verilog.v | ||
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// generated by newgenasym Wed Sep 29 14:02:10 2010
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// generated by newgenasym Mon Oct 18 14:31:48 2010
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module pont_diode (ac, ac1, \v+ , \v- );
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| trunk/librairies/polytech_ge/pont_diode/entity/vhdl.vhd | ||
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-- generated by newgenasym Wed Sep 29 14:02:10 2010
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-- generated by newgenasym Mon Oct 18 14:31:48 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity pont_diode is
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entity PONT_DIODE is
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port (
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AC: INOUT STD_LOGIC;
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AC1: INOUT STD_LOGIC;
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\v+\: INOUT STD_LOGIC;
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\v-\: INOUT STD_LOGIC);
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end pont_diode;
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end PONT_DIODE;
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Formats disponibles : Unified diff
ajout symbole 2