root/branch/KANAAN/sp4c12/sp4c1/c1/uart0.c @ 787
| 787 | frkanaan | /***********************************************************************/
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/* */
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/* FILE :uart0.c */
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/* DATE :Thu, Jun 03, 2021 */
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/* DESCRIPTION :main program file. */
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/* CPU GROUP :87B */
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/* */
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/* This file is generated by Renesas Project Generator (Ver.4.18). */
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/* NOTE:THIS IS A TYPICAL EXAMPLE. */
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/***********************************************************************/
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void uart0_init (void)
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{
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//i flag=0;
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smd0_u0mr=0; /* Serial I/O mode select bit */
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smd1_u0mr=0; /* Serial I/O mode select bit */
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smd2_u0mr=1; /* Serial I/O mode select bit */
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ckdir_u0mr=1; /* Internal/external clock select bit */
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stps_u0mr=1; /* Stop bit length select bit */
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pry_u0mr=1; /* Odd/even parity select bit */
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prye_u0mr=1; /* Parity enable bit */
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iopol_u0mr=0; /* TxD RxD I/O polarity switch bit */
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u0smr=0x00;
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u0smr2=0x00;
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u0smr3=0x00;
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u0smr4=0x00;
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clk0_u0c0=1;
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clk1_u0c0=0;
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crs_u0c0=0;
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crd_u0c0=0;
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nch_u0c0=0;
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ckpol_u0c0=0;
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uform_u0c0=0;
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u0brg=0x20;
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te_u0c1=0;
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re_u0c1=0;
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u0irs_u0c1=1;
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u0rrm_u0c1=0;
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u0lch_u0c1=1;
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u0ere_u0c1=0;
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ilvl0_s0tic=0;
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ilvl1_s0tic=0;
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ilvl2_s0tic=1;
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ir_s0tic = 0;
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ilvl0_s0ric=0;
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ilvl1_s0ric=0;
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ilvl2_s0ric=1;
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ir_s0ric = 0;
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//i flag=1;
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te_u0c1=1;
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re_u0c1=1;
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}
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void uart0_tx(char c)
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{
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}
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char uart0_rx(void)
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{
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}
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