|
/***********************************************************************/
|
|
/* */
|
|
/* FILE :uart0.c */
|
|
/* DATE :Thu, Jun 03, 2021 */
|
|
/* DESCRIPTION :main program file. */
|
|
/* CPU GROUP :87B */
|
|
/* */
|
|
/* This file is generated by Renesas Project Generator (Ver.4.18). */
|
|
/* NOTE:THIS IS A TYPICAL EXAMPLE. */
|
|
/***********************************************************************/
|
|
|
|
void uart0_init (void)
|
|
{
|
|
//i flag=0;
|
|
|
|
smd0_u0mr=0; /* Serial I/O mode select bit */
|
|
smd1_u0mr=0; /* Serial I/O mode select bit */
|
|
smd2_u0mr=1; /* Serial I/O mode select bit */
|
|
ckdir_u0mr=1; /* Internal/external clock select bit */
|
|
stps_u0mr=1; /* Stop bit length select bit */
|
|
pry_u0mr=1; /* Odd/even parity select bit */
|
|
prye_u0mr=1; /* Parity enable bit */
|
|
iopol_u0mr=0; /* TxD RxD I/O polarity switch bit */
|
|
|
|
u0smr=0x00;
|
|
u0smr2=0x00;
|
|
u0smr3=0x00;
|
|
u0smr4=0x00;
|
|
|
|
clk0_u0c0=1;
|
|
clk1_u0c0=0;
|
|
crs_u0c0=0;
|
|
crd_u0c0=0;
|
|
nch_u0c0=0;
|
|
ckpol_u0c0=0;
|
|
uform_u0c0=0;
|
|
|
|
u0brg=0x20;
|
|
|
|
te_u0c1=0;
|
|
re_u0c1=0;
|
|
u0irs_u0c1=1;
|
|
u0rrm_u0c1=0;
|
|
u0lch_u0c1=1;
|
|
u0ere_u0c1=0;
|
|
|
|
ilvl0_s0tic=0;
|
|
ilvl1_s0tic=0;
|
|
ilvl2_s0tic=1;
|
|
ir_s0tic = 0;
|
|
|
|
ilvl0_s0ric=0;
|
|
ilvl1_s0ric=0;
|
|
ilvl2_s0ric=1;
|
|
ir_s0ric = 0;
|
|
|
|
//i flag=1;
|
|
|
|
te_u0c1=1;
|
|
re_u0c1=1;
|
|
}
|
|
|
|
|
|
void uart0_tx(char c)
|
|
{
|
|
|
|
}
|
|
|
|
|
|
char uart0_rx(void)
|
|
{
|
|
|
|
}
|