Révision 827
Ajouté par anclaud il y a presque 4 ans
| branch/CLAUD/sp4c12/SP41c/SP41c/uart0.h | ||
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/***********************************************************************/
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/* */
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/* FILE :SP41c.c */
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/* DATE :Thu, Jun 03, 2021 */
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/* DESCRIPTION :main program file. */
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/* CPU GROUP :87B */
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/* */
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/* This file is generated by Renesas Project Generator (Ver.4.18). */
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/* NOTE:THIS IS A TYPICAL EXAMPLE. */
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/***********************************************************************/
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void uart0_init (void);
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void uart0_tx(char c);
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char uart0_rx(void);
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void uart0_init()
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{
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/*
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smd0_u0mr = 1
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smd1_u0mr = 0
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smd2_u0mr = 1
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ckdir_u0mr = 0
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stps_u0mr = 0
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pry_u0mr = 0
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prye_u0mr = 0
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iopol_u0mr = 0
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*/
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u0mr = 0x05;
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/*
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clk0_u0c0 = 1
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clk1_u0c0 = 0
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crs_u0c0 = 0
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txept_u0c0 = 0
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crd_u0c0 = 1
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nch_u0c0 = 0
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ckpol_u0c0 = 0
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uform_u0c0 = 0
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*/
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u0c0 = 0x11;
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/*
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te_u0c1 = 1
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ti_u0c1 = 0
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re_u0c1 = 1
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ri_u0c1 = 0
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uilrs_u0c1 = 0
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uirrm_u0c1 = 0
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uilch_u0c1 = 0
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sclkstpb_u0c1 = 0
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uiere_u0c1 = 0
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*/
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u0c1 = 0x05;
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u0brg = 0x20; // m = 32
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// Config port 6 pd6 = 0x08
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pd6_1 = 0;
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pd6_2 = 0;
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ps0_1 = 0;
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ps0_2 = 0;
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ps0_3 = 1;
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}
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void uart0_tx(char c)
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{
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te_u0c1 = 1;
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u0tb = c;
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te_u0c1 = 0;
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}
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char uart0_rx()
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{
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return u0rb;
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}
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| branch/CLAUD/sp4c12/SP41c/SP41c/uart0.c | ||
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/***********************************************************************/
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/* */
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/* FILE :SP41c.c */
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/* DATE :Thu, Jun 03, 2021 */
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/* DESCRIPTION :main program file. */
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/* CPU GROUP :87B */
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/* */
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/* This file is generated by Renesas Project Generator (Ver.4.18). */
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/* NOTE:THIS IS A TYPICAL EXAMPLE. */
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/***********************************************************************/
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#include "sfr32c87.h"
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#include "uart0.h"
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void main(void)
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{
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char c;
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uart0_init();
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//c = '3';
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while(1)
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{
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c = uart0_rx();
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uart0_tx(c);
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}
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}
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Formats disponibles : Unified diff
Commit fichiers uart0.c et .h