root/branch/DEMAGALHAES/sp4c12/sp4c1/sp4c1/sp4c1.c @ 837
| 765 | rademagalh | /***********************************************************************/
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/* */
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/* FILE :sp4c1.c */
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/* DATE :Thu, Jun 03, 2021 */
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/* DESCRIPTION :main program file. */
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/* CPU GROUP :87B */
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/* */
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/* This file is generated by Renesas Project Generator (Ver.4.18). */
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/* NOTE:THIS IS A TYPICAL EXAMPLE. */
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/***********************************************************************/
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| 781 | rademagalh | #include "sfr32c87.h"
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void uart0_init(void)
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| 765 | rademagalh | {
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| 781 | rademagalh | // U0MR REGISTER : DES BITS SMD2 A SMD0
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smd0_u0mr = 1;
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smd1_u0mr = 0;
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smd2_u0mr = 1;
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| 765 | rademagalh | ||
| 781 | rademagalh | // U0MR REGISTER : CLOCK SELECT (CKDIR) STOP BIT LENGHT (STPS) PARITY ENABLE (PRYE) TXD RXD INVERTED (IOPOL)
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ckdir_u0mr = 0;
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stps_u0mr = 0;
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prye_u0mr = 0;
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iopol_u0mr = 0;
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// U0SMR - USMR4 REGISTER :
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u0smr = 0x00;
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u0smr2 = 0x00;
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u0smr3 = 0x00;
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u0smr4 = 0x00;
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// U0C0 REGISTER :
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clk0_u0c0 = 1;
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clk1_u0c0 = 0;
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//ckpol_u0c0 = 0;
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crs_u0c0 = 0;
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crd_u0c0 = 0;
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nch_u0c0 = 0;
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// U0BRG REGISTER (BAUD RATE) :
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u0brg = 0x20;
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// U0C1 REGISTER :
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te_u0c1 = 0;
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re_u0c1 = 0;
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// PIN SETTINGS
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pd6_1=0;
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pd6_2=0;
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ps0_1 = 0;
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ps0_2 = 0;
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ps0_3 = 1;
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| 765 | rademagalh | }
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| 781 | rademagalh | ||
void uart0_tx(char c)
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{
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crs_u0c0 = 0;
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crd_u0c0 = 1;
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te_u0c1 = 1;
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u0tb = c;
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te_u0c1 = 0;
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}
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char uart0_rx()
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{
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char c;
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crs_u0c0 = 0;
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crd_u0c0 = 1;
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re_u0c1 = 1;
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c = u0rb;
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return c;
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}
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void main(void)
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{
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char sequence[26]={'A','B','C','D','E','F','G','H','I','J','K','L','M','N','O','P','Q','R','S','T','U','V','W','X','Y','Z'};
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int i=0,j=0;
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char c;
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uart0_init();
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while(1)
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{
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c = uart0_rx();
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uart0_tx(c);
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}
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}
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