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root/branch/DEMAGALHAES/sp4c12/sp4c1/sp4c1/sp4c1.c @ 837

/***********************************************************************/
/* */
/* FILE :sp4c1.c */
/* DATE :Thu, Jun 03, 2021 */
/* DESCRIPTION :main program file. */
/* CPU GROUP :87B */
/* */
/* This file is generated by Renesas Project Generator (Ver.4.18). */
/* NOTE:THIS IS A TYPICAL EXAMPLE. */
/***********************************************************************/

#include "sfr32c87.h"

void uart0_init(void)
{
// U0MR REGISTER : DES BITS SMD2 A SMD0
smd0_u0mr = 1;
smd1_u0mr = 0;
smd2_u0mr = 1;
// U0MR REGISTER : CLOCK SELECT (CKDIR) STOP BIT LENGHT (STPS) PARITY ENABLE (PRYE) TXD RXD INVERTED (IOPOL)
ckdir_u0mr = 0;
stps_u0mr = 0;
prye_u0mr = 0;
iopol_u0mr = 0;
// U0SMR - USMR4 REGISTER :
u0smr = 0x00;
u0smr2 = 0x00;
u0smr3 = 0x00;
u0smr4 = 0x00;
// U0C0 REGISTER :
clk0_u0c0 = 1;
clk1_u0c0 = 0;
//ckpol_u0c0 = 0;
crs_u0c0 = 0;
crd_u0c0 = 0;
nch_u0c0 = 0;
// U0BRG REGISTER (BAUD RATE) :
u0brg = 0x20;
// U0C1 REGISTER :
te_u0c1 = 0;
re_u0c1 = 0;
// PIN SETTINGS
pd6_1=0;
pd6_2=0;
ps0_1 = 0;
ps0_2 = 0;
ps0_3 = 1;
}
void uart0_tx(char c)
{
crs_u0c0 = 0;
crd_u0c0 = 1;
te_u0c1 = 1;
u0tb = c;
te_u0c1 = 0;
}

char uart0_rx()
{
char c;
crs_u0c0 = 0;
crd_u0c0 = 1;
re_u0c1 = 1;
c = u0rb;
return c;
}


void main(void)
{
char sequence[26]={'A','B','C','D','E','F','G','H','I','J','K','L','M','N','O','P','Q','R','S','T','U','V','W','X','Y','Z'};
int i=0,j=0;
char c;
uart0_init();
while(1)
{
c = uart0_rx();
uart0_tx(c);
}
}
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